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LM3218SE 데이터시트(PDF) 5 Page - National Semiconductor (TI) |
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LM3218SE 데이터시트(HTML) 5 Page - National Semiconductor (TI) |
5 / 16 page Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics tables. Note 2: All voltages are with respect to the potential at the GND pins. The LM3218 is designed for mobile phone applications where turn-on after power-up is controlled by the system controller and where requirements for a small package size overrule increased die size for internal Under Voltage Lock-Out (UVLO) circuitry. Thus, it should be kept in shutdown by holding the EN pin low until the input voltage exceeds 2.7V. Note 3: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at T J = 150°C (typ.) and disengages at TJ = 125°C (typ.). Note 4: The Human body model is a 100 pF capacitor discharged through a 1.5 k Ω resistor into each pin. (MIL-STD-883 3015.7) The machine model is a 200 pF capacitor discharged directly into each pin. Note 5: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be de- rated. Maximum ambient temperature (T A-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C), the maximum power dissipation of the device in the application (P D-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θJA), as given by the following equation: T A-MAX = TJ-MAX-OP – (θJA × PD-MAX). Note 6: Junction-to-ambient thermal resistance ( θ JA) is taken from thermal measurements, performed under the conditions and guidelines set forth in the JEDEC standard JESD51-7. A 4–layer, 4" x 4", 2/1/1/2 oz. Cu board as per JEDEC standards is used for the measurements. Note 7: Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm. Due to the pulsed nature of the testing T A = TJ for the electrical characteristics table. Note 8: The parameters in the electrical characteristics table are tested under open loop conditions at PV IN = VDD = 3.6V unless otherwise specified. For performance over the input voltage range and closed-loop results, refer to the datasheet curves. Note 9: Shutdown current includes leakage current of PFET. Note 10: I Q specified here is when the part is not switching. For operating quiescent current at no load, refer to datasheet curves. Note 11: Current limit is built-in, fixed, and not adjustable. Electrical Characteristic table reflects open loop data (FB = 0V and current drawn from SW pin ramped up until cycle by cycle limit is activated). Refer to System Characteristics table for maximum output current. Note 12: Ripple voltage should be measured at C OUT electrode on a well-designed PC board and using the suggested inductor and capacitors. Note 13: National Semiconductor recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper ESD handling procedures can result in damage. Note 14: Linearity limits are ±3% or ±50 mV whichever is larger. 5 www.national.com |
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