74AHC259D datasheet(9/17 Pages) NXP

부품명	74AHC259D

상세설명	8-bit addressable latch

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9 / 17 page

74AHC_AHCT259_2

Product data sheet

Rev. 02 — 15 May 2008

9 of 17

NXP Semiconductors

74AHC259; 74AHCT259

8-bit addressable latch

[1]

Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V).

[2]

tpd is the same as tPLH and tPHL.

[3]

tpd is the same as tPHL only.

[4]

CPD is used to determine the dynamic power dissipation (PD in µW).

PD =CPD × VCC2 × fi × N+ Σ(CL × VCC2 × fo) where:

fi = input frequency in MHz;

fo = output frequency in MHz;

CL = output load capacitance in pF;

VCC = supply voltage in V;

N = number of inputs switching;

Σ(C

L × VCC

2

× f

o) = sum of the outputs.

11. Waveforms

tsu

set-up time

D, An to LE; see Figure 9

and Figure 10

4.0

-

4.0

-

4.0

-

ns

th

hold time

D, An to LE; see Figure 9

and Figure 10

1.0

-

1.0

-

1.0

-

ns

CPD

power

dissipation

capacitance

fi = 1 MHz; VI = GND to VCC

[4]

-17

-

pF

Table 8.

Dynamic characteristics …continued

Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11.

Symbol Parameter

Conditions

25

°C

−40 °C to +85 °C −40 °C to +125 °C Unit

Min

Typ[1] Max

Min

Max

Min

Max

Measurement points are given in Table 9.

VOL and VOH are typical voltage output levels that occur with the output load.

Fig 5.

Data input to output propagation delays

001aah123

D input

Qn output

tPHL

tPLH

GND

VCC

VM

VOH

VOL

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NXP Semiconductors	74AHC259D	95Kb / 20P	8-bit addressable latch 2000 Mar 14

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74AHC259D 데이터시트(PDF) 9 Page - NXP Semiconductors

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