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DS4250P+ 데이터시트(PDF) 5 Page - Maxim Integrated Products

부품명 DS4250P+
부품 상세설명  DS4-XO Series Crystal Oscillators
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제조업체  MAXIM [Maxim Integrated Products]
홈페이지  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

DS4250P+ 데이터시트(HTML) 5 Page - Maxim Integrated Products

  DS4250P+ Datasheet HTML 1Page - Maxim Integrated Products DS4250P+ Datasheet HTML 2Page - Maxim Integrated Products DS4250P+ Datasheet HTML 3Page - Maxim Integrated Products DS4250P+ Datasheet HTML 4Page - Maxim Integrated Products DS4250P+ Datasheet HTML 5Page - Maxim Integrated Products DS4250P+ Datasheet HTML 6Page - Maxim Integrated Products DS4250P+ Datasheet HTML 7Page - Maxim Integrated Products DS4250P+ Datasheet HTML 8Page - Maxim Integrated Products  
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DS4-XO Series Crystal Oscillators
_______________________________________________________________________________________
5
Detailed Description
The devices consist of a fundamental-mode, AT-cut
crystal and a synthesizer IC that can synthesize any
one of these frequencies: 77.76MHz, 125MHz,
150MHz, 155.52MHz, 156.25MHz, 160MHz, 250MHz,
300MHz, 311.04MHz, 312.5MHz, and 622.08MHz.
All devices support two types of differential output dri-
vers: LVDS and LVPECL. When the OE signal is low,
LVPECL outputs go to the PECL_BIAS level of
VCC - 2.0V, while the LVDS outputs are a logical one.
See Figures 2 and 3 for an LVDS and LVPECL output
timing diagram.
Additional Information
For more available frequencies, refer to the DS4106
data sheet at www.maxim-ic.com/DS4106.
X1
X2
TRI-
STATE
PHASE
DET
FILTER
LC-VCO
/n
OUTSELN
/m
OUTDRV
VCC
GND
OE
OUTP
OUTN
DS4125–DS4776
Figure 1. Functional Diagram
OE
OUTP
tP1A
tPA1
0.7 x VCC
0.3 x VCC
OUTN
Figure 2. LVDS Output Timing Diagram When OE Is Enabled
and Disabled
OE
OUTP
PECL_BIAS
PECL_BIAS
PECL_BIAS
PECL_BIAS
OUTN
0.7 x VCC
0.3 x VCC
tPAZ
tPZA
Figure 3. LVPECL Output Timing Diagram When OE Is Enabled
and Disabled


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