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KMPC8568ECVTAQJGA 데이터시트(Datasheet) 4 Page - Freescale Semiconductor, Inc

부품명 KMPC8568ECVTAQJGA
상세내용  MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications
PDF  139 Pages
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제조사  FREESCALE [Freescale Semiconductor, Inc]
홈페이지  http://www.freescale.com
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MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1
4
Freescale Semiconductor
MPC8568E Overview
— Byte-accessible ECC uses read-modify-write transaction accesses for smaller-than-cache-line
accesses.
1.2.2
e500 Coherency Module (ECM) and Address Map
The e500 coherency module (ECM) provides a mechanism for I/O-initiated transactions to snoop the bus
between the e500 core and the integrated L2 cache in order to maintain coherency across local cacheable
memory. It also provides a flexible switch-type structure for core- and I/O-initiated transactions to be
routed or dispatched to target modules on the device.
The MPC8568E supports a flexible 36-bit physical address map. Conceptually, the address map consists of
local space and external address space. The local address map is supported by eight local access windows
that define mapping within the local 36-bit (64-Gbyte) address space.
The MPC8568E can be made part of a larger system address space through the mapping of translation
windows. This functionality is included in the address translation and mapping units (ATMUs). Both
inbound and outbound translation windows are provided. The ATMUs allows the MPC8568E to be part of
larger address maps such as the PCI or PCI Express 64-bit address environment and the RapidIO
environment.
1.2.3
QUICC Engine
Integrated 8-port L2 Ethernet switch
— 8 connection ports of 10/100 Mbps MII/RMII & one CPU internal port
— Each port supports four priority levels
— Priority levels used with VLAN tags or IP TOS field to implement QoS
— QoS types of traffic, such as voice, video, and data
Includes support for the following protocols:
— ATM SAR up to 622 Mbps (OC-12) full duplex, with ATM traffic shaping (ATF TM4.1) for
up to 64K ATM connections
— ATM AAL1 structured and unstructured Circuit Emulation Service (CES 2.0)
— IMA and ATM Transmission convergence sub-layer
— ATM OAM handling features compatible with ITU-T I.610
— PPP, Multi-Link (ML-PPP), Multi-Class (MC-PPP) and PPP mux in accordance with the
following RFCs: 1661, 1662, 1990, 2686 and 3153
— IP termination support for IPv4 and IPv6 packets including TOS, TTL and header checksum
processing
— ATM (AAL2/AAL5) to Ethernet (IP) interworking
— Extensive support for ATM statistics and Ethernet RMON/MIB statistics.
— 256 channels of HDLC/Transparent or 128 channels of SS#7
Includes support for the following serial interfaces:
— Two UL2/POS-PHY interfaces with 124 Multi-PHY addresses on UTOPIA interface each or
31 Multi-PHY addresses on the POS interface each.




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