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KMPC8568VTAQGJA 데이터시트(Datasheet) 9 Page - Freescale Semiconductor, Inc

부품명 KMPC8568VTAQGJA
상세내용  MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications
PDF  139 Pages
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제조사  FREESCALE [Freescale Semiconductor, Inc]
홈페이지  http://www.freescale.com
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MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1
Freescale Semiconductor
9
MPC8568E Overview
1.2.12
Programmable Interrupt Controller (PIC)
The MPC8568E PIC implements the logic and programming structures of the OpenPIC architecture,
providing for external interrupts (with fully nested interrupt delivery), message interrupts, internal-logic
driven interrupts, and global high-resolution timers. Up to 16 programmable interrupt priority levels are
supported.
The PIC can be bypassed to allow use of an external interrupt controller.
1.2.13
DMA Controller, I2C, DUART, and Local Bus Controller
The MPC8568E provides an integrated four-channel DMA controller, which can transfer data between any
of its I/O or memory ports or between two devices or locations on the same port. The DMA controller also:
Allows chaining (both extended and direct) through local memory-mapped chain descriptors.
Scattering, gathering, and misaligned transfers are supported. In addition, stride transfers and
complex transaction chaining are supported.
Local attributes such as snoop and L2 write stashing can be specified.
There are two I2C controllers. These synchronous, multimaster buses can be connected to additional
devices for expansion and system development.
The DUART supports full-duplex operation and is compatible with the PC16450 and PC16550
programming models. 16-byte FIFOs are supported for both the transmitter and the receiver.
The MPC8568E local bus controller (LBC) port allows connections with a wide variety of external
memories, DSPs, and ASICs. Three separate state machines share the same external pins and can be
programmed separately to access different types of devices. The general-purpose chip select machine
(GPCM) controls accesses to asynchronous devices using a simple handshake protocol. The user
programmable machine (UPM) can be programmed to interface to synchronous devices or custom ASIC
interfaces. The SDRAM controller provides access to standard SDRAM. Each chip select can be configured
so that the associated chip interface can be controlled by the GPCM, UPM, or SDRAM controller. All may
exist in the same system. The local bus controller supports the following features:
Multiplexed 32-bit address and data bus operating at up to 133 MHz
Eight chip selects support eight external slaves
Up to eight-beat burst transfers
32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
Three protocol engines available on a per-chip-select basis
Parity support
Default boot ROM chip select with configurable bus width (8, 16, or 32 bits)
Supports zero-bus-turnaround (ZBT) RAM
1.2.14
Power Management
In addition to low-voltage operation and dynamic power management, which automatically minimizes
power consumption of blocks when they are idle, four power consumption modes are supported: full on,
doze, nap, and sleep.




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