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KMPC8568ECVTAUGJA 데이터시트(Datasheet) 18 Page - Freescale Semiconductor, Inc

부품명 KMPC8568ECVTAUGJA
상세내용  MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications
PDF  139 Pages
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제조사  FREESCALE [Freescale Semiconductor, Inc]
홈페이지  http://www.freescale.com
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 18 page
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MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1
18
Freescale Semiconductor
RESET Initialization
5
RESET Initialization
This section describes the AC electrical specifications for the RESET initialization timing requirements of
the MPC8568E. Table 10 provides the RESET initialization AC timing specifications for the DDR
SDRAM component(s).
Table 11 provides the PLL lock times.
6
DDR and DDR2 SDRAM
This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the
MPC8568E. Note that DDR SDRAM is GVDD(typ) = 2.5 V and DDR2 SDRAM is GVDD(typ) = 1.8 V.
Table 10. RESET Initialization Timing Specifications
Parameter/Condition
Min
Max
Unit
Notes
Required assertion time of HRESET
100
μs—
Minimum assertion time for SRESET
3
SYSCLKs
1
PLL input setup time with stable SYSCLK before HRESET negation
100
μs—
Input setup time for POR configs (other than PLL config) with respect to
negation of HRESET
4
SYSCLKs
1
Input hold time for all POR configs (including PLL config) with respect to
negation of HRESET
2
SYSCLKs
1
Maximum valid-to-high impedance time for actively driven POR configs with
respect to negation of HRESET
5
SYSCLKs
1
Notes:
1. SYSCLK is the primary clock input for the MPC8568E.
Table 11. PLL Lock Times
Parameter/Condition
Min
Max
Unit
Notes
Platform PLL lock times
100
μs—
QE PLL lock times
100
μs—
CPU PLL lock times
100
μs—
PCI PLL lock times
100
μs—
Local bus PLL
100
μs—




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