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KMPC8568VTANJJA 데이터시트(PDF) 15 Page - Freescale Semiconductor, Inc |
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KMPC8568VTANJJA 데이터시트(HTML) 15 Page - Freescale Semiconductor, Inc |
15 / 139 page MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 15 Input Clocks 4 Input Clocks 4.1 System Clock Timing Table 7 provides the system clock (SYSCLK) AC timing specifications for the MPC8568E. eTSEC Ethernet MII 0.01 W Multiply with number of the interfaces GMII/TBI 0.07 W RGMII/RTBI 0.04 W eTSEC FIFO I/O 16b, 200 MHz 0.20 W Multiply with number of the interfaces 16b, 155 MHz 0.16 W 8b, 200 MHz 0.11 W 8b, 155 MHz 0.08 W QE UCC MII/RMII 0.01 W Multiply with number of the interfaces If UCC is programmed for other protocols, scale Ethernet power dissipation to the number of signals and the clock rate GMII/TBI 0.07 W RGMII/RTBI 0.04 W Note: This is the power for each individual interface. The power must be calculated for each interface being utilized. Table 7. SYSCLK AC Timing Specifications At recommended operating conditions (see Table 3) with OVDD = 3.3 V ± 165 mV. Parameter/Condition Symbol Min Typical Max Unit Notes SYSCLK frequency fSYSCLK — — 166 MHz 1 SYSCLK cycle time tSYSCLK 6.0 — — ns — SYSCLK rise and fall time tKH, tKL 0.61.0 2.3ns 2 SYSCLK duty cycle tKHK/tSYSCLK 40 — 60 % 3 Table 6. Typical MPC8568E I/O Power Dissipation (continued) Interface Parameters GVDD BVDD OVDD LVDD TVDD XVDD Unit Comment 2.5 V 1.8 V 3.3 V 2.5 V 3.3 V 2.5 V 3.3 V 2.5 V |
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