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TLE6254-3G 데이터시트(PDF) 4 Page - Infineon Technologies AG |
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TLE6254-3G 데이터시트(HTML) 4 Page - Infineon Technologies AG |
4 / 26 page Data Sheet 4 Rev. 2.1, 2007-08-09 TLE6254-3G Figure 1 Pin Configuration PG-DSO-14 (top view) Table 1 Pin Definitions and Functions Pin No. Symbol Function 1INH Inhibit output; for controlling an external voltage regulator 2TxD Transmit data input; integrated pull-up, LOW: bus becomes dominant, HIGH: bus becomes recessive 3RxD Receive data output; integrated pull-up, LOW: bus is dominant, HIGH: bus is recessive 4NERR Error flag output; integrated pull-up, LOW: bus error (in normal operation mode), further functions see Table 2 5NSTB Not stand-by input; digital control input to select operation modes, see Figure 4 6ENT Enable transfer input; digital control input to select operation modes, see Figure 4 7WK Wake-Up input; if level of V WAKE changes the device indicates a wake-up from low power mode by switching the RxD outputs LOW and switching the INH output HIGH (in sleep mode), see Table 2 AEP03323N.VSD 7 6 5 4 3 2 1 INH TxD RxD NERR NSTB ENT WK 8 9 10 11 12 13 14 GND CANL CANH RTL RTH VS V CC TLE6254 -3G |
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