전자부품 데이터시트 검색엔진 |
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LB11870 데이터시트(PDF) 3 Page - Sanyo Semicon Device |
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LB11870 데이터시트(HTML) 3 Page - Sanyo Semicon Device |
3 / 14 page No. 7256 -3/14 LB11870 Continued from preceding page. Parameter Symbol Conditions Ratings Unit min typ max [Phase Comparator Output] High-level output voltage VPDH IOH = –100 µA VREG – 0.2 VREG – 0.1 V Low-level output voltage VPDL IOL = 100 µA 0.2 0.3 V Output source current IPD+ VPD = VREG/2 –0.5 mA Output sink current IPD– VPD = VREG/2 1.5 mA [Lock Detection Output] Output saturation voltage VOL (LD) ILD = 10 mA 0.15 0.5 V Output leakage current IL (LD) VO = VCC 10 µA [Error Amplifier Block] Input offset voltage VIO (ER) Design target value –10 10 mV Input bias current IB (ER) –1 1 µA Output H level voltage VOH (ER) IOH = –500 µA VREG – 1.2 VREG – 0.9 V Output L level current VOL (ER) IOL = 500 µA 0.9 1.2 V DC bias level VB (ER) –5% VREG/2 5% V [Current limiter Circuit] Drive gain 1 GDF1 When the phase is locked 0.4 0.5 0.6 deg Drive gain 2 GDF2 When not locked 0.8 1.0 1.2 deg Limiter voltage VRF VCC-VM 0.45 0.5 0.55 V [Thermal Shutdown Operation] Thermal shutdown operating temperature TSD Design target value (junction temperature) 150 175 °C Hysteresis width ∆TSD Design target value (junction temperature) 40 °C [Low-Voltage Protection] Operating voltage VSD 8.1 8.45 8.9 V Hysteresis width ∆VSD 0.2 0.35 0.5 V [CLD Circuit] External capacitor charge current ICLD –6 –4.3 –3 µA Operating voltage VH (CLD) 3.25 3.5 3.75 V [CLK Pin] External input frequency fI (CLK) 0.1 10 kHz High-level input voltage VIH (CLK) 3.5 VREG V Low-level input voltage VIL (CLK) 0 1.5 V Input open voltage VIO (CLK) VREG – 0.5 VREG V Hysteresis width VIS (CLK) 0.35 0.5 0.65 V High-level input current IIH (CLK) VCLK = VREG –10 0 10 µA Low-level input current IIL (CLK) VCLK = 0 V –280 –210 µA [S/S Pin] High-level input voltage VIH (SS) 3.5 VREG V Low-level input voltage VIL (SS) 0 1.5 V Input open voltage VIO (SS) VREG – 0.5 VREG V Hysteresis width VIS (SS) 0.35 0.5 0.65 V High-level input current IIH (SS) VS/S = VREG –10 0 10 µA Low-level input current IIL (SS) VS/S = 0 V –280 –210 µA [BRSEL Pin] High-level input voltage VIH (BRSEL) 3.5 VREG V Low-level input voltage VIL (BRSEL) 0 1.5 V Input open voltage VIO (BRSEL) VREG – 0.5 VREG V High-level input current IIH (BRSEL) VBRSEL = VREG –10 0 10 µA Low-level input current IIL (BRSEL) VBRSEL = 0 V –220 –160 µA |
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