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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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LM27402SQ 데이터시트(PDF) 3 Page - National Semiconductor (TI) |
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LM27402SQ 데이터시트(HTML) 3 Page - National Semiconductor (TI) |
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3 / 32 page  Pin Descriptions eTSSOP Pin # LLP Pin # Name Description 1 16 CS+ Non-inverting input to the current sense comparator. 2 15 CS- Inverting input to the current sense comparator with +10 µA offset current for adjustable current limit setpoint. 3 1 SS/TRACK Soft-start or tracking input. A startup rate can be defined with the use of an external soft-start capacitor from SS/TRACK to GND. A +3 µA current source charges the soft-start capacitor to set the output voltage rise time during startup. SS/TRACK can also be controlled with an external voltage source for tracking. SS/TRACK should not exceed the voltage on VDD. 4 2 FB Inverting input to the error amplifier to set the output voltage and compensate the voltage mode control loop. 5 3 COMP Output of the internal error amplifier. The COMP voltage is compared to an internally generated ramp of the PWM comparator to establish the duty cycle command. 6 4 FADJ Frequency adjust pin. The switching frequency can be set to a predetermined rate by connecting a resistor between FADJ and GND. 7 6 SYNC Frequency synchronization pin. An external clock signal can be applied to SYNC to set the switching frequency. The SYNC frequency must be greater than the frequency set by the FADJ pin. If the signal is not present, the switching frequency will decrease to the frequency set by the FADJ resistor. SYNC should not exceed the voltage on VDD and should be grounded if not used. 8 5 EN LM27402 enable pin. Apply a voltage typically higher than 1.17V to EN and the LM27402 will begin to switch if VIN and VDD have exceeded the UVLO voltage. A hysteresis of 100 mV on EN provides noise immunity. EN is internally tied to VDD through a 2 µA pullup current source. EN should not exceed the voltage on VDD. 9 8 PGOOD Power good output flag. PGOOD is connected to the drain of a pulldown FET. The PGOOD pin is typically connected to VDD through a pull-up resistor. 10 7 VIN Input supply rail. The VIN operating range is 3V to 20V and is connected to the input rail through an RC filter. 11 9 GND Common ground. 12 10 VDD Internal sub-regulated 4.5V bias supply. VDD is used to supply the voltage on CBOOT to facilitate high-side FET switching. Connect a 1 µF ceramic capacitor from VDD to GND as close as possible to the LM27402. VDD cannot be connected to a separate voltage rail. However, VDD can be connected to VIN to provide increased gate drive only if V IN ≤ 5.5V. A 1Ω, 1 µF input filter can be used for increased noise rejection. 13 11 LG Low-side N-FET gate drive. 14 12 SW Switch-node connection and return path for the high-side gate driver. 15 14 HG High-side N-FET gate drive. 16 13 CBOOT High-side gate driver supply rail. Connect a ceramic capacitor from CBOOT to SW and a Schottky diode from VDD to CBOOT. EP EP EP Exposed Pad. The EP must be connected to GND but cannot be used as the primary ground connection. Use multiple vias under this pad for optimal thermal performance. 3 www.national.com |
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