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PK10N256VLK72 데이터시트(PDF) 49 Page - Freescale Semiconductor, Inc

부품명 PK10N256VLK72
상세설명  K10 Sub-Family Data Sheet
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제조업체  FREESCALE [Freescale Semiconductor, Inc]
홈페이지  http://www.freescale.com
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PK10N256VLK72 데이터시트(HTML) 49 Page - Freescale Semiconductor, Inc

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First data
Last data
First data
Data
Last data
Data
DS15
DS10
DS9
DS16
DS11
DS12
DS14
DS13
DSPI_SS
DSPI_SCK
(CPOL=0)
DSPI_SOUT
DSPI_SIN
Figure 20. DSPI Classic SPI Timing — Slave Mode
6.8.3 SDHC Specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface.
Table 38. SDHC switching specifications
Num
Symbol
Description
Min.
Max.
Unit
Card input clock
SD1
fpp
Clock frequency (low speed)
0
400
kHz
fpp
Clock frequency (SD\SDIO full speed)
0
25
MHz
fpp
Clock frequency (MMC full speed)
0
20
MHz
fOD
Clock frequency (identification mode)
0
400
kHz
SD2
tWL
Clock low time
7
ns
SD3
tWH
Clock high time
7
ns
SD4
tTLH
Clock rise time
3
ns
SD5
tTHL
Clock fall time
3
ns
SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD6
tOD
SDHC output delay (output valid)
-5
6.5
ns
SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD7
tTHL
SDHC input setup time
5
ns
SD8
tTHL
SDHC input hold time
0
ns
Peripheral operating requirements and behaviors
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
Preliminary
49


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