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LC35V1000BTS-70U 데이터시트(PDF) 8 Page - Sanyo Semicon Device |
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LC35V1000BTS-70U 데이터시트(HTML) 8 Page - Sanyo Semicon Device |
8 / 9 page Notes: 1. The times tCOD1, tCOD2, tOOD, and tWOD are stipulated as the times until the output reaches the high-impedance state. They are not stipulated by output voltage level. 2. Do not apply reverse phase signals to the data outputs when the data outputs are in the output state. 3. tWP is the period that CE1 and WE are at the low level and CE2 is at the high level, and is defined as the time from the fall of WE until the rise of CE1 or WE or the fall of CE2, whichever occurs first. 4. tCW1 and tCW2 are the period that CE1 and WE are at the low level and CE2 is at the high level, and are defined as the time from the fall of CE1 or the rise of CE2 to the rise of either CE1 or WE or the fall of CE2, whichever occurs first. 5. The data outputs go to the high-impedance state when any one of the following states hold: OE is at the high level, CE1 is at the high level, CE2 is at the low level, or WE is at the low level. 6. If OE is at the high level during the write cycle, the data outputs will go to the high-impedance state. No. 7056-8/9 LC35V1000BM, BTS-70U Parameter Symbol Conditions Ratings Unit min typ max Data retention supply voltage VDR1 VCE1 ≥ VCC – 0.2 V, VCE2 ≥ VCC – 0.2 V or VCE2 ≤ 0.2 V 2.0 3.6 V VDR2 VCE2 ≤ 0.2 V 2.0 3.6 V VCC = 3.0 V, VCE1 ≥ VCC – 0.2 V, –40°C to +85°C 16 Data retention supply current ICCDR1 VCE2 ≥ VCC – 0.2 V, –40°C to +70°C 8 µA or VCE2 ≤ 0.2 V +25°C 0.05 Chip enable setup time tCDR 0 ns Chip enable hold time tR 5 ms Data Retention Characteristics at Ta = –40 to +85°C Data Retention Waveforms (1) (CE1 control) Note: * Ta = +25°C Data retention mode Data Retention Waveforms (2) (CE2 control) Data retention mode |
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