LC680100A

No.6830-11/16

6. DRAM Timing at Ta = -20 to 70

°C, VSS = 0V, VDD = 3.0 to 3.6V, with the load in Figure 14

Ratings

Parameter

Symbol

Pins

Conditions

Min.

Typ.

Max.

Unit

Address (ROW) delay

time

tAROW

A27 to A0

Figure 9, Figure 10

75

Address (COL) delay

time

tACOL

A27 to A0

Figure 9, Figure 10

55

Address (COL) hold

time

tCOLA

A27 to A0

Figure 9, Figure 10

70

RAS delay time

tARAS

RAS

Figure 9, Figure 10

65

RAS hold time

tRASA

RAS

Figure 9, Figure 10

50

DMXS delay time

tDMXSR

DMXS

Figure 9, Figure 10

70

DMXS hold time

tDMXSC

DMXS

Figure 9, Figure 10

50

CASL•CASU delay

time

tACAS(L/U)

CASU

Figure 9, Figure 10

65

CASL•CASU hold

time

tCAS(L/U)A

CASU

Figure 9, Figure 10

50

ns

Read data set up time

(2)

tsRD2

D15 to D0

Figure 9

30

Read data hold time

(2)

thRD2

Figure 9

0

ns

WRL•WRU delay

time

tAWR(L/U)

WRU

Figure 10

45

WRL•WRU hold time

tWR(L/U)A

WRU

Figure 10

50

Write data delay time

(2)

tdWD2

D15 to D0,

WRU

Figure 10

70

Write data hold time

(2)

thWD2

D15 to D0,

WRU

Figure 10

0

ns

Table 1. Guaranteed Value for the Ceramic Oscillators

Oscillator

Manufacturer

Oscillator

C1

C2

4MHZ (External Capacitor)

CSA4. OOMG

33pF

33pF

4MHZ (Capacitor built-in)

CST4. OOMGW

(30pF)

(30pF)

8MHZ (External Capacitor)

CSA8. OOMTZ

33pF

33pF

8MHZ (Capacitor built-in)

Murata

CST8. OOMTW

(30pF)

(30pF)