전자부품 데이터시트 검색엔진 |
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LC66516B 데이터시트(PDF) 11 Page - Sanyo Semicon Device |
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LC66516B 데이터시트(HTML) 11 Page - Sanyo Semicon Device |
11 / 21 page Continued from preceding page. Note: 1. With the output Nch transistor off in shared I/O ports with the open-drain output specifications. These pins cannot be used as input pins if the CMOS output specifications are selected. 2. With the output Nch transistor off in shared I/O ports with the open-drain output specifications. The rating for the pull-up output specification pins is stipulated in terms of the output pull-up current IPO. These pins cannot be used as input pins if the CMOS output specifications are selected. 3. With the output Nch transistor off for CMOS output specification pins. 4. With the output Nch transistor off for pull-up output specification pins. 5. With the output Nch transistor off for open-drain output specification pins. 6. Reset state Figure 1 External Clock Input Waveform Figure 2 Ceramic Oscillator Circuit Figure 3 Oscillator Stabilization Period Table 1 Guaranteed Ceramic Oscillator Constants No. 5484-11/21 LC66354C, 66356C, 66358C Parameter Symbol Conditions min typ max Unit Note [Pulse conditions] INT0: Figure 6, conditions under which the INT0 INT0 high and low-level t IOH, tIOL interrupt can be accepted, conditions under 2 Tcyc which the timer 0 event counter or pulse width measurement input can be accepted High and low-level pulse widths t IIH, tIIL INT1, INT2: Figure 6, conditions under which 2 Tcyc for interrupt inputs other than INT0 the corresponding interrupt can be accepted PIN1 high and low-level t PINH, tPINL PIN1: Figure 6, conditions under which the 2 Tcyc pulse widths timer 1 event counter input can be accepted RES high and low-level t RSH, tRSL RES: Figure 6, conditions under which reset 3 Tcyc pulse widths can be applied. Comparator response speed TRS PD: Figure 7, VDD = 3.0 to 5.5 V 20 ms Operating current drain I DD OP VDD: 4-MHz ceramic oscillator 3.0 5.0 mA 6 VDD: 4-MHz external clock 3.0 5.0 mA Halt mode current drain I DDHALT VDD: 4-MHz ceramic oscillator 1.0 2.0 mA VDD: 4-MHz external clock 1.0 2.0 mA Hold mode current drain IDDHOLD VDD: VDD = 1.8 to 5.5 V 0.01 10 µA 4 MHz C1 = 33 pF ± 10% 4 MHz C1 = 33 pF ± 10% (Murata Mfg. Co., Ltd.) C2 = 33 pF ± 10% (Kyocera Corporation) C2 = 33 pF ± 10% CSA4.00MG Rd = 0 Ω KBR4.0MS Rd = 0 Ω textL OPEN (OSC2) OSC1 textR textF VSS VDD 0.2VDD 0.8VDD 1/fext textH External clock OSC2 OSC1 C1 C2 Rd Ceramic oscillator VDD OSC 0V Oscillator unstable period t Stable oscillation Operating V minimum value CFS DD |
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