ISL29028A

4

FN7721.1

February 8, 2011

IRDR Sink Current

95

110

125

mA

IRDR Sink Current

220

mA

0.001

1

µA

Acceptable Voltage Range on IRDR Pin

Register bit PROX_DR = 0

0.5

4.3

V

100

µs

0.51

V

400

kHz

1.7

3.63

V

SCL and SDA Input Low Voltage

0.55

V

SCL and SDA Input High Voltage

1.25

V

SDA Current Sinking Capability

3

5

mA

INT Current Sinking Capability

3

5

mA

(

4

mA/V

NOTES:

7. Nonlinearity is defined as: [(Measured Counts at 53 lux)-(Expected Counts at 53 lux)]/4095. Expected counts are calculated using an endpoint linear-

fit trendline from measurements at 0 lux and 90 lux.

8. An LED is used in production test. The LED irradiance is calibrated to produce the same DATA count against a fluorescent light source of the same lux

level

9. An 850nm infrared LED is used to test PROX/IR sensitivity in an internal test mode.

11. For ALS applications under light-distorting glass, please see the section titled ALS Range 1 Considerations.

PARAMETER

DESCRIPTION

CONDITION

MIN

TYP

MAX

UNIT

(Note 12).

PARAMETER

DESCRIPTION

CONDITION

MIN

TYP MAX

UNIT

1.7

3.63

V

SCL Clock Frequency

400

kHz

SCL and SDA Input Low Voltage

0.55

V

SCL and SDA Input High Voltage

1.25

V

Hysteresis of Schmitt Trigger Input

V

Low-level Output Voltage (Open-drain) at 4mA Sink

Current

0.4

V

Input Leakage for each SDA, SCL pin

-10

10

µA

Pulse Width of Spikes that must be Suppressed by

the Input Filter

50

ns

SCL Falling Edge to SDA Output Data Valid

900

ns

Capacitance for each SDA and SCL pin

10

pF

Hold Time (Repeated) START Condition

After this period, the first clock pulse is

generated

600

ns

LOW Period of the SCL Clock

Measured at the 30% of VDD crossing

1300

ns

HIGH period of the SCL Clock

600

ns

Set-up Time for a Repeated START Condition

600

ns

Data Hold Time

30

ns