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LC74950BG 데이터시트(PDF) 9 Page - Sanyo Semicon Device |
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LC74950BG 데이터시트(HTML) 9 Page - Sanyo Semicon Device |
9 / 37 page LC74950BG No.A1647-9/37 Pin Connection 1) ADC and its peripherals 2) PLL and its pereipherals 3) Output pin (recommended) 4) Power supplies The analog A** and digital D** power supplies must be supplied separately without fail. In addition, the power supply for the PLL circuit must also be provided separately as it will affect the jitter characteristics of the PLL circuit. For ADC power supply, it is desirable to provide separate power for eachof the ADC channel. AVDD33_PLL : Must be separated by L components, etc. ADC2AVDD33A : Separating by L components, etc. recommended ADC1AVDD33A : Separating by L components, etc. recommended ADC0AVDD33A : Separating by L components, etc. recommended 5) Unused pin treatment YGIN0, 1/CBIN0, 1/CRIN0, 1: Open PDWN: Pull up CHRGPMP: Open (when PLL is not in use) ***OUT* (e.g., YGOUT0): Open HSIN/VSIN: Must always be configured for input. RESET: Must always be configured for input. COAST: Must be connected to DVSS. TEST, SCANEN, SCANMOD: DVSS CLKIN: DVSS HSOUT, VSOUT, DEOUT: Open SVO, ATB: Open * The specified voltage of power must be applied to each of the power supply pin even if it is not to be used (PLL is not to be used, for example). 10 μF 10 μF 0.1 μF 0.1 μF 0.1 μF VRTx VRBx VRTx: VRT0, VRT1, VRT2 VRBx: VRB0, VRB1, VRB2 0.1 μF xINx YGIN0, YGIN1 CRIN0, CRIN1 CBIN0, CBIN1 Terminal resistor 0.068 μF 3.3k Ω 0.0039 μF CHRGPMP CBOUT0-3 5pF |
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