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LC89201 데이터시트(PDF) 5 Page - Sanyo Semicon Device |
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LC89201 데이터시트(HTML) 5 Page - Sanyo Semicon Device |
5 / 9 page 2. DTE Interface Pins 3. Eye Pattern Interface Pins 4. V.24 (RS-232C) Interface Pins 5. Analog Signal Pins No. 4974-5/8 LC89201 Pin No. Symbol I/O Function 29 D0 28 D1 27 D2 26 D3 B Data bus to host CPU 25 D4 23 D5 22 D6 21 D7 20 A0 19 A1 18 A2 I Address bus to host CPU 17 A3 16 A4 30 CSB I Chip select signal 32 READB I Interface memory read signal 33 WRITEB I Interface memory write signal 34 IREQB O Interrupt request to host CPU 15 RESETB I System reset signal Pin No. Symbol I/O Function 67 EYECLK O Timing clock for generating eye pattern data. This may be used as the shift clock for an external shift register. 68 EYESYNC O Eye pattern synchronization signal 66 EYEX O Eye pattern data serial outputs (8 bits, MSB first) 65 EYEY Pin No. Symbol I/O Function 57 RTSB I Request to send signal. The low level at this pin starts transmission; the high level suspends it. 59 CTSB O Clear to send signal. The low level at this pin signals the availability of data for transmission; the high level indicates that the data is invalid. 58 RLSDB O Received line signal data signal. The low level at this pin gives the timing for transferring the data received to the terminal. 61 TXD I Transmit data input 60 RXD O Receive data output 62 DCLK O Transmission data clock output Pin No. Symbol I/O Function 39 TXA O Transmitter analog output 44 RXA I Receiver analog input 43 AUXIN I Auxiliary analog input 40 OPA2P I 41 OPA2M I Transmission buffer input/output pins. (For details, see circuit diagram.) 42 OPA2O O 47 OPA1P I 46 OPA1M I Reception buffer input/output pins (For details, see circuit diagram.) 45 OPA1O O 49 PGCI I Reception gain adjustment circuit input. (For details, seecircuit diagram.) 48 PGCO O Reception gain adjustment circuit output. |
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