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TPS56121 데이터시트(PDF) 10 Page - Texas Instruments |
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TPS56121 데이터시트(HTML) 10 Page - Texas Instruments |
10 / 22 page 0 0.4 0.8 1.2 1.6 Time (ms) 2.0 Calibration Time(1.9 ms) 0.7 V 1.3 V V SS_INT V EN/SS TPS56121 SLUSAH4 – MARCH 2011 www.ti.com APPLICATION INFORMATION Introduction The TPS56121 is a 15-A high performance synchronous buck converter with two integrated N-channel NexFET ™ power MOSFETs. The device implements a voltage-mode control with voltage feed-forward compensation that responds instantly to input voltage change. Pre-bias capability eliminates concerns about damaging sensitive loads. Voltage Reference The 600-mV bandgap cell is internally connected to the non-inverting input of the error amplifier. The reference voltage is trimmed with the error amplifier in a unity gain configuration to remove amplifier offset from the final regulation voltage. The 1% tolerance on the reference voltage allows the user to design a very accurate power supply. Figure 19. Startup Sequence and Timing Enable Functionality, Startup Sequence and Timing After input power is applied, an internal 40- μA current source begins to charge the soft-start capacitor connected from EN/SS to GND. When the voltage across that capacitor increases to 0.7 V, it enables the internal BP regulator followed by a calibration. Total calibration time is approximately 1.9 ms. See Figure 19. During the calibration, the device performs the following two functions. COMP Pin Impedance Sensing The device samples the impedance at the COMP pin and determines the appropriate operating switching frequency. If there is no resistor connected from the COMP pin to GND, the switching frequency is set to the default value of 500 kHz. If a resistor of 40.2 k Ω ± 10% is connected from the COMP pin to GND, the switching frequency is set to 300 kHz. Alternatively, if a resistor of 13.3 K ± 10% is connected from the COMP pin to GND, the switching frequency is set to 1 MHz. After a 1.1-ms time period, the COMP pin is then brought low for 0.8 ms. This ensures that the feedback loop is preconditioned at startup and no sudden output rise occurs at the output of the converter when it is allowed to start switching. Overcurrent Protection (OCP) setting The device sources 10 μA (typical) to the resistor connected from the ILIM pin to GND. The voltage developed across that resistor multiplied by a factor of 2 is then sampled and latched off internally as the OCP trip level for the low-side FET until one cycles the input or toggles the EN/SS. The voltage at EN/SS is internally clamped to 1.3 V before and/or during calibration to minimize the discharging 10 Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS56121 |
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