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FAN6206MY 데이터시트(PDF) 3 Page - Fairchild Semiconductor |
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FAN6206MY 데이터시트(HTML) 3 Page - Fairchild Semiconductor |
3 / 15 page © 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6206 • Rev. 1.0.2 3 Marking Information Figure 3. Top Mark Pin Configuration Figure 4. Pin Configuration Pin Definitions Pin # Name Description 1,2 LPC1, LPC2 Winding detection. This pin is used to detect the voltage on the winding during the on-time period of the primary GATE. An internal current source, ICHG, is determined according to the voltage on the DET pin. 3 SN Synchronized signal to turn on SR. This pin is used to receive the “XN” signal from the primary side to turn off the SR gate. 4 SP Synchronized signal to turn on SR. This pin is used to receive the “XP” signal from the primary- side to turn-on the SR gate. 5 VDD Power supply pin. The threshold voltages for startup and turn-off are 8.5V and 7.5V, respectively. 6 GATE2 Driver output for freewheeling synchronous rectifier MOSFET. 7 GND Ground 8 GATE1 Driver output for rectifying synchronous rectifier MOSFET. F : Fairchild Logo Z: Plant Code X: Year Code Y: Week Code TT: Package Type T: M=SOP P: Y: Green Package M: Manufacture Flow Code |
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