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STK15C88-SF45ITR 데이터시트(PDF) 3 Page - Cypress Semiconductor |
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STK15C88-SF45ITR 데이터시트(HTML) 3 Page - Cypress Semiconductor |
3 / 17 page STK15C88 Document Number: 001-50593 Rev. *C Page 3 of 17 Pin Configurations Figure 1. Pin Diagram - 28-pin SOIC Table 1. Pin Definitions - 28-pin SOIC Pin Name Alt I/O Type Description A0–A14 Input Address Inputs. Used to select one of the 32,768 bytes of the nvSRAM. DQ0-DQ7 Input or Output Bidirectional Data I/O lines. Used as input or output lines depending on operation. WE W Input Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the I/O pins is written to the specific address location. CE E Input Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip. OE G Input Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles. Deasserting OE HIGH causes the I/O pins to tristate. VSS Ground Ground for the Device. The device is connected to ground of the system. VCC Power Supply Power Supply Inputs to the Device. [+] Feedback |
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