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DAC3484IRKDR 데이터시트(PDF) 4 Page - Texas Instruments |
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DAC3484IRKDR 데이터시트(HTML) 4 Page - Texas Instruments |
4 / 82 page DAC3484 SLAS749A – MARCH 2011 – REVISED JULY 2011 www.ti.com PIN FUNCTIONS (continued) PIN I/O DESCRIPTION NAME NO. A7, A8, B9, LVDS positive input data bits 0 through 15. Internal 100 Ω termination resistor. Data format relative to B10, A12, DATACLKP/N clock is Double Data Rate (DDR). A13, A14, D15P is most significant data bit (MSB) A15, B17, D[15..0]P I D0P is least significant data bit (LSB) B18, B19, B20, A23, A24, B23, The order of the bus can be reversed via config2 revbus bit. B24 B7, B8, A10, A11, B11, B12, B13, B14, A19, D[15..0]N I LVDS negative input data bits 0 through 15. (See D[15:0]P description above) A20, A21, A22, B21, B22, A26, A27 DACCLKP A3 I Positive external LVPECL clock input for DAC core with a self-bias. DACCLKN B3 I Complementary external LVPECL clock input for DAC core. (see the DACCLKP description) A35, A39, DAC core supply voltage. (1.2 V). It is recommended to isolate this supply from CLKVDD and DACVDD I A43 DIGVDD. LVDS positive input data clock. Internal 100 Ω termination resistor. Input data D[15:0]P/N is latched DATACLKP A16 I on both edges of DATACLKP/N (Double Data Rate). DATACLKN B15 I LVDS negative input data clock. (See DATACLKP description) A6, A9, A25, DIGVDD I Digital supply voltage. (1.2 V). It is recommended to isolate this supply from CLKVDD and DACVDD. A28 Used as external reference input when internal reference is disabled through config27 extref_ena = EXTIO A34 I/O ‘1’. Used as internal reference output when config27 extref_ena = ‘0’ (default). Requires a 0.1 μF decoupling capacitor to AGND when used as reference output. LVDS frame indicator positive input. Internal 100 Ω termination resistor. The main functions of this input are to reset the FIFO pointer or to be used as a syncing source. These two functions are captured with the rising edge of DATACLKP/N. The signal captured by the FRAMEP B16 I falling edge of DATACLKP/N can be used as a block parity bit. The FRAMEP/N signal should be edge-aligned with D[15:0]P/N. Additionally it is used to indicate the beginning of the frame. FRAMEN A18 I LVDS frame indicator negative input. (See the FRAMEP description) C1, C2, C3, GND C4, Thermal I These pins are ground for all supplies. Pad IOUTAP B39 O A-Channel DAC current output. Connect directly to ground if unused. IOUTAN B38 O A-Channel DAC complementary current output. Connect directly to ground if unused. IOUTBP B36 O B-Channel DAC current output. Connect directly to ground if unused. IOUTBN B37 O B-Channel DAC complementary current output. Connect directly to ground if unused. IOUTCP B35 O C-Channel DAC current output. Connect directly to ground if unused. IOUTCN B34 O C-Channel DAC complementary current output. Connect directly to ground if unused. IOUTDP B32 O D-Channel DAC current output. Connect directly to ground if unused. IOUTDN B33 O D-Channel DAC complementary current output. Connect directly to ground if unused. IOVDD B6, A17, B25 I Supply voltage for all digital I/O. (3.3 V) LPF A1 I/O PLL loop filter connection. If not using the clock multiplying PLL, the LPF pin can be left unconnected. LVPECL output strobe positive input. This positive/negative pair is captured with the rising edge of OSTRP A2 I DACCLKP/N. It is used for multiple DAC synchronization. If unused it can be left unconnected. OSTRN B2 I LVPECL output strobe negative input. (See the OSTRP description) Optional LVDS positive input parity bit. The PARITYP/N LVDS pair has an internal 100 Ω termination PARITYP B26 I resistor. If unused it can be left unconnected. PARITYN A29 I Optional LVDS negative input parity bit. PLLAVDD B1 I PLL analog supply voltage. (3.3 V) 4 Copyright © 2011, Texas Instruments Incorporated |
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