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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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FM25V05 데이터시트(PDF) 3 Page - Ramtron International Corporation |
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FM25V05 데이터시트(HTML) 3 Page - Ramtron International Corporation |
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3 / 16 page  FM25V05 - 512Kb SPI FRAM Rev. 2.0 May 2010 Page 3 of 16 Overview The FM25V05 is a serial F-RAM memory. The memory array is logically organized as 65,536 x 8 and is accessed using an industry standard Serial Peripheral Interface or SPI bus. Functional operation of the F-RAM is similar to Serial Flash. The major differences between the FM25V05 and a Serial Flash with the same pinout are the F-RAM’s superior write performance, very high endurance, and lower power consumption. Memory Architecture When accessing the FM25V05, the user addresses 64K locations of 8 data bits each. These data bits are shifted serially. The addresses are accessed using the SPI protocol, which includes a chip select (to permit multiple devices on the bus), an op-code, and a two- byte address. The complete address of 16-bits specifies each byte address uniquely. Most functions of the FM25V05 either are controlled by the SPI interface or are handled automatically by on-board circuitry. The access time for memory operation is essentially zero, beyond the time needed for the serial protocol. That is, the memory is read or written at the speed of the SPI bus. Unlike Serial Flash, it is not necessary to poll the device for a ready condition since writes occur at bus speed. So, by the time a new bus transaction can be shifted into the device, a write operation will be complete. This is explained in more detail in the interface section. Users expect several obvious system benefits from the FM25V05 due to its fast write cycle and high endurance as compared to Serial Flash. In addition there are less obvious benefits as well. For example in a high noise environment, the fast-write operation is less susceptible to corruption than Serial Flash since it is completed quickly. By contrast, Serial Flash requiring milliseconds to write is vulnerable to noise during much of the cycle. Serial Peripheral Interface – SPI Bus The FM25V05 employs a Serial Peripheral Interface (SPI) bus. It is specified to operate at speeds up to 40MHz. This high-speed serial bus provides high performance serial communication to a host microcontroller. Many common microcontrollers have hardware SPI ports allowing a direct interface. It is quite simple to emulate the port using ordinary port pins for microcontrollers that do not. The FM25V05 operates in SPI Mode 0 and 3. Protocol Overview The SPI interface is a synchronous serial interface using clock and data pins. It is intended to support multiple devices on the bus. Each device is activated using a chip select. Once chip select is activated by the bus master, the FM25V05 will begin monitoring the clock and data lines. The relationship between the falling edge of /S, the clock and data is dictated by the SPI mode. The device will make a determination of the SPI mode on the falling edge of each chip select. While there are four such modes, the FM25V05 supports only modes 0 and 3. Figure 2 shows the required signal relationships for modes 0 and 3. For both modes, data is clocked into the FM25V05 on the rising edge of C and data is expected on the first rising edge after /S goes active. If the clock starts from a high state, it will fall prior to the first data transfer in order to create the first rising edge. The SPI protocol is controlled by op-codes. These op-codes specify the commands to the device. After /S is activated the first byte transferred from the bus master is the op-code. Following the op-code, any addresses and data are then transferred. Certain op-codes are commands with no subsequent data transfer. The /S must go inactive after an operation is complete and before a new op-code can be issued. There is one valid op-code only per active chip select. SPI Mode 0: CPOL=0, CPHA=0 SPI Mode 3: CPOL=1, CPHA=1 Figure 2. SPI Modes 0 & 3 |
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