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LC863240C 데이터시트(PDF) 3 Page - Sanyo Semicon Device |
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3 / 21 page LC863264C/56C/48C/40C/32C/28C/24C/20C/16C No.A0115-3/21 Bus Cycle Time / Instruction-Cycle Time Bus cycle time Instruction cycle time System clock oscillation Oscillation frequency Voltage 0.424 µs 0.848 µs Internal VCO (Ref : X’tal 32.768kHz) 14.156MHz 4.5V to 5.5V 7.5 µs 15.0 µs Internal RC 800kHz 4.5V to 5.5V 183.1 µs 366.2 µs Crystal 32.768kHz 4.5V to 5.5V Ports • Input / Output Ports : 5 ports (28 terminals) Data direction programmable in nibble units : 1 port (8 terminals) (If the N-ch open drain output is selected by option, the corresponding port data can be read in output mode.) Data direction programmable for each bit individually : 4 ports (20 terminals) AD converter • 4 channels×8-bit AD converters Serial interfaces • IIC-bus compliant serial interface (Multi-master type) Consists of a single built-in circuit with two I/O channels. The two data lines and two clock lines can be connected internally. • Synchronous 8-bit serial interface PWM output • 3 channels×7-bit PWM Timer • Timer 0 : 16-bit timer/counter With 2-bit prescaler + 8-bit programmable prescaler Mode 0 : Two 8-bit timers with a programmable prescaler Mode 1 : 8-bit timer with a programmable prescaler + 8-bit counter Mode 2 : 16-bit timer with a programmable prescaler Mode 3 : 16-bit counter The resolution of timer is 1 tCYC. • Timer 1 : 16-bit timer/PWM Mode 0 : Two 8-bit timers Mode 1 : 8-bit timer + 8-bit PWM Mode 2 : 16-bit timer Mode 3 : Variable bit PWM (9 to 16 bits) In mode0/1, the resolution of Timer1/PWM is 1 tCYC In mode2/3, the resolution is selectable by program; tCYC or 1/2 tCYC • Base timer Generate every 500ms overflow for a clock application (using 32.768kHz crystal oscillation for the base timer clock) Generate every 976 µs, 3.9ms, 15.6ms, 62.5ms overflow (using 32.768kHz crystal oscillation for the base timer clock) Clock for the base timer is selectable from 32.768kHz crystal oscillation, system clock or programmable prescaler output of Timer 0 Remote control receiver circuit (connected to the P73/INT3/T0IN terminal) • Noise rejection function • Polarity switching Watchdog timer External RC circuit is required Interrupt or system reset is activated when the timer overflows ROM correction function Max 128 bytes / 2 addresses |
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