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74FCT388915T13JG 데이터시트(PDF) 5 Page - Integrated Device Technology |
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5 / 10 page COMMERCIALTEMPERATURERANGE IDT74FCT388915T 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (3-STATE) 5 SWITCHING CHARACTERISTICS OVER OPERATING RANGE Symbol Parameter Condition(1) Min. Max. Unit tRISE/FALL Rise/Fall Time Load = 50 Ω to VCC/2, CL = 20pF 0.2(2) 2ns All Outputs (between 0.8V and 2V) tPULSEWIDTH(3) Output Pulse Width Load = 50 Ω to VCC/2, CL = 20pF 0.5tCYCLE –0.8(5) 0.5tCYCLE+ 0.8(5) ns Q, Q, Q/2 outputs(3) Q0-Q4, Q5, Q/2, @ 1.5V tPULSEWIDTH Output Pulse Width 0.5tCYCLE–1(5) 0.5tCYCLE+ 1(5) ns 2QOutput(3) 2Q @ 1.5V tPD SYNC input to FEEDBACK delay Load = 50 Ω to VCC/2, CL = 20pF +0.1 +1.3 ns SYNC-FEEDBACK(3) (measured at SYNC0 or 1 and FEEDBACK input pins) 0.1µF from LF to Analog GND(5) tSKEWr Output to Output Skew between outputs 2Q, Q0-Q4, Load = 50 Ω to VCC/2, CL = 20pF — 600 ps (rising)(3,4) Q/2 (rising edges only) tSKEWf Output to Output Skew — 250 ps (falling)(3,4) between outputs Q0-Q4 (falling edges only) tSKEWall(3,4) Output to Output Skew — 800 ps 2Q, Q/2, Q0-Q4 rising, Q5 falling tLOCK(6) Time required to acquire Phase-Lock from time 1(2) 10 ms SYNC input signal is received tPZH OutputEnableTime 3(2) 14 ns tPZL OE/ RST (LOW-to-HIGH) to Q, 2Q, Q/2, Q tPHZ OutputDisableTime 3(2) 14 ns tPLZ OE/ RST (HIGH-to-LOW) to Q, 2Q, Q/2, Q GENERAL AC SPECIFICATION NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested. 3. These specifications are guaranteed but not production tested. 4. Under equally loaded conditions, as specified under test conditions and at a fixed temperature and voltage. 5. tCYCLE = 1/frequency at which each output (Q, Q, Q/2 or 2Q) is expected to run. 6. With VCC fully powered-on and an output properly connected to the FEEDBACK pin, tLOCK Max. is with C1 = 0.1µF, tLOCK Min. is with C1 = 0.01µF. (Where C1 is loop filter capacitor shown in Figure 2). 7. The wiring diagrams and written explanations of Figure 3 demonstrate the input and output frequency relationships for various possible feedback configurations. The allowable SYNC input range to stay in the phase-locked condition is also indicated. There are two allowable SYNC frequency ranges, depending on whether FREQ_SEL is HIGH or LOW. Also it is possible to feed back the Q5 output, thus creating a 180° phase shift between the SYNC input and the Q outputs. The table below summarizes the allowable SYNC frequency range for each possible configuration. FREQ_SEL Feedback Allowable SYNC Input Corresponding 2Q Output Phase Relationship of the Q Outputs Level Output Frequency Range (MHZ) Frequency Range to Rising SYNC Edge HIGH Q/2 10 to (2x_Q fMAX Spec)/4 40 to (2Q fMAX Spec) 0° HIGH Any Q (Q0-Q4) 20 to (2x_Q fMAX Spec)/2 40 to (2Q fMAX Spec) 0° HIGH Q5 20 to (2x_Q fMAX Spec)/2 40 to (2Q fMAX Spec) 180° HIGH 2X_Q 40 to (2x_Q fMAX Spec) 40 to (2Q fMAX Spec) 0° LOW Q/2 5 to (2x_Q fMAX Spec)/8 20 to (2Q fMAX Spec)/2 0° LOW Any Q (Q0-Q4) 10 to (2x_Q fMAX Spec)/4 20 to (2Q fMAX Spec)/2 0° LOW Q5 10 to (2x_Q fMAX Spec)/4 20 to (2Q fMAX Spec)/2 180° LOW 2X_Q 20 to (2x_Q fMAX Spec)/2 20 to (2Q fMAX Spec)/2 0° |
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