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SI4126 데이터시트(PDF) 6 Page - Silicon Laboratories |
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SI4126 데이터시트(HTML) 6 Page - Silicon Laboratories |
6 / 34 page Si4136/Si4126 6 Rev. 1.41 Figure 1. SCLK Timing Diagram Table 4. Serial Interface Timing (V DD = 2.7 to 3.6 V, TA = –40 to 85 °C) Parameter1 Symbol Test Condition Min Typ Max Unit SCLK Cycle Time tclk Figure 1 40 — — ns SCLK Rise Time tr Figure 1 — — 50 ns SCLK Fall Time t f Figure 1 — — 50 ns SCLK High Time th Figure 1 10 — — ns SCLK Low Time tl Figure 1 10 — — ns SDATA Setup Time to SCLK 2 t su Figure 2 5 — — ns SDATA Hold Time from SCLK 2 thold Figure 2 0 — — ns SEN to SCLKDelay Time2 ten1 Figure 2 10 — — ns SCLK to SENDelay Time2 t en2 Figure 2 12 — — ns SEN to SCLKDelay Time2 ten3 Figure 2 12 — — ns SEN Pulse Width tw Figure 2 10 — — ns Notes: 1. All timing is referenced to the 50% level of the waveform, unless otherwise noted. 2. Timing is not referenced to 50% level of the waveform. See Figure 2. SCLK 80% 50% 20% tr tf t h t l t clk |
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