전자부품 데이터시트 검색엔진 |
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SI52146 데이터시트(PDF) 5 Page - Silicon Laboratories |
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SI52146 데이터시트(HTML) 5 Page - Silicon Laboratories |
5 / 20 page Si52146 Preliminary Rev. 0.1 5 Table 2. AC Electrical Specifications Parameter Symbol Condition Min Typ Max Unit Crystal Long-term Accuracy LACC Measured at VDD/2 differential — — 250 ppm Clock Input CLKIN Duty Cycle TDC Measured at VDD/2 47 — 53 % CLKIN Rise and Fall Times TR/TF Measured between 0.2 VDD and 0.8 VDD 0.5 — 4.0 V/ns CLKIN Cycle to Cycle Jitter TCCJ Measured at VDD/2 — — 250 ps CLKIN Long Term Jitter TLTJ Measured at VDD/2 — — 350 ps Input High Voltage VIH XIN/CLKIN pin 2 — VDD+0.3 V Input Low Voltage VIL XIN/CLKIN pin — — 0.8 V Input High Current IIH XIN/CLKIN pin, VIN = VDD — — 35 uA Input Low Current IIL XIN/CLKIN pin, 0 < VIN <0.8 –35 — — uA DIFF at 0.7 V DIFF Duty Cycle TDC Measured at 0 V differential 45 — 55 % Any DIFF Clock Skew from the Earliest Bank to the Latest Bank TSKEW(win dow) Measured at 0 V differential — — 50 ps DIFF Cycle to Cycle Jitter TCCJ Measured at 0 V differential — 35 50 ps Output PCIe Gen1 REFCLK Phase Jitter RMSGEN1 Includes PLL BW 1.5–22 MHz, ζ = 0.54, Td=10 ns, Ftrk=1.5 MHz with BER = 1E-12 040 108 ps Output PCIe Gen2 REFCLK Phase Jitter RMSGEN2 Includes PLL BW 8–16 MHz, Jitter Peaking = 3 dB, ζ = 0.54, Td=12 ns), Low Band, F < 1.5 MHz 02 3.0 ps Output PCIe Gen2 REFCLK Phase Jitter RMSGEN2 Includes PLL BW 8–16 MHz, Jitter Peaking = 3 dB, ζ = 0.54, Td=12 ns), High Band, 1.5 MHz < F < Nyquist 02 3.1 ps Output Phase Jitter Impact— PCIe Gen3 RMSGEN3 Includes PLL BW 2–4 MHz, CDR = 10 MHz) 00.5 1.0 ps DIFF Long Term Accuracy LACC Measured at 0 V differential — — 100 ppm DIFF Rising/Falling Slew Rate TR/TF Measured differentially from ±150 mV 1— 8 V/ns Voltage High VHIGH —— 1.15 V Voltage Low VLOW –0.3 — — V Crossing Point Voltage at 0.7 V Swing VOX 300 — 550 mV Enable/Disable and Setup Clock Stabilization from Power-up TSTABLE —— 1.8 ms Stopclock Set-up Time TSS 10.0 — — ns |
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