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Q67121-C923 데이터시트(PDF) 39 Page - Siemens Semiconductor Group

부품명 Q67121-C923
상세설명  C16x-Family of High-Performance CMOS 16-Bit Microcontrollers
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제조업체  SIEMENS [Siemens Semiconductor Group]
홈페이지  http://www.siemens.com/
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C165
Semiconductor Group
38
AC Characteristics (cont’d)
Demultiplexed Bus
V
CC = 5 V ± 10 %;
V
SS = 0 V
T
A = 0 to +70 ˚C
for SAB-C165-LM, SAB-C165-RM, SAB-C165-LF, SAB-C165-RF
T
A = -40 to +85 ˚C
for SAF-C165-LM
C
L (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF
C
L (for Port 6, CS) = 100 pF
ALE cycle time = 4 TCL + 2
t
A + tC + tF (100 ns at 20-MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock
= 20 MHz
Variable CPU Clock
1/2TCL = 1 to 20 MHz
Unit
min.
max.
min.
max.
ALE high time
t
5
CC 15 +
t
A
TCL - 10 +
t
A
–ns
Address setup to ALE
t
6
CC 10 +
t
A
TCL - 15 +
t
A
–ns
ALE falling edge to RD,
WR (with RW-delay)
t
8
CC 15 +
t
A
TCL - 10
+
t
A
–ns
ALE falling edge to RD,
WR (no RW-delay)
t
9
CC -10 +
t
A
-10
+
t
A
–ns
RD, WR low time
(with RW-delay)
t
12
CC 40 +
t
C
2TCL - 10
+
t
C
–ns
RD, WR low time
(no RW-delay)
t
13
CC 65 +
t
C
3TCL - 10
+
t
C
–ns
RD to valid data in
(with RW-delay)
t
14
SR –
30 +
t
C
2TCL - 20
+
t
C
ns
RD to valid data in
(no RW-delay)
t
15
SR –
55 +
t
C
3TCL - 20
+
t
C
ns
ALE low to valid data in
t
16
SR –
55
+
t
A + tC
3TCL - 20
+
t
A + tC
ns
Address to valid data in
t
17
SR –
70
+ 2
t
A + tC
4TCL - 30
+ 2
t
A + tC
ns
Data hold after RD
rising edge
t
18
SR 0
0–ns
Data float after RD rising
edge (with RW-delay)
t
20
SR –
35 +
t
F
2TCL - 15
+
t
F
ns
Data float after RD rising
edge (no RW-delay)
t
21
SR –
15 +
t
F
TCL - 10
+
t
F
ns
Data valid to WR
t
22
CC 35 +
t
C
2TCL - 15
+
t
C
–ns
Data hold after WR
t
24
CC 15 +
t
F
TCL - 10 +
t
F
–ns
ALE rising edge after RD,
WR
t
26
CC -10 +
t
F
-10
+
t
F
–ns


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