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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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Q67127-C2029 데이터시트(PDF) 42 Page - Siemens Semiconductor Group |
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Q67127-C2029 데이터시트(HTML) 42 Page - Siemens Semiconductor Group |
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42 / 85 page  Semiconductor Group 42 1997-12-01 C505 / C505C C505A / C505CA 10-Bit A/D Converter (C505A and C505CA only) The C505 includes a high performance / high speed 10-bit A/D-Converter (ADC) with 8 analog input channels. It operates with a successive approximation technique and uses self calibration mechanisms for reduction and compensation of offset and linearity errors. The A/D converter provides the following features: – 8 multiplexed input channels (port 1), which can also be used as digital inputs/outputs – 10-bit resolution – Single or continuous conversion mode – Internal start-of-conversion trigger capability – Interrupt request generation after each conversion – Using successive approximation conversion technique via a capacitor array – Built-in hidden calibration of offset and linearity errors The 10-bit ADC uses two clock signals for operation : the conversion clock fADC (=1/tADC) and the input clock fIN (=1/tIN). fADC is derived from the C505 system clock fOSC which is applied at the XTAL pins. The input clock fIN is equal to fOSC The conversion fADC clock is limited to a maximum frequency of 2 MHz. Therefore, the ADC clock prescaler must be programmed to a value which assures that the conversion clock does not exceed 2 MHz. The prescaler ratio is selected by the bits ADCL1 and ADCL0 of SFR ADCON1. Figure 19 10-Bit A/D Converter Clock Selection MCS03635 f OSC MUX Clock Prescaler Conversion Clock Input Clock f ADC IN f ADCL1 A / D Converter Condition: ADC max f < 2 MHz IN f = f OSC = CLP 1 32 8 4 16 ADCL0 MCU System Clock Rate ( fOSC) fIN [MHz] Prescaler Ratio fADC [MHz] ADCL1 ADCL0 2 MHz 2 ÷ 4 0.5 0 0 6 MHz 6 ÷ 4 1.5 0 0 8 MHz 8 ÷ 4 200 12 MHz 12 ÷ 8 1.5 0 1 16 MHz 16 ÷ 8 201 20 MHz 20 ÷ 16 1.25 1 0 |
유사한 부품 번호 - Q67127-C2029 |
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유사한 설명 - Q67127-C2029 |
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