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AZP63 데이터시트(PDF) 3 Page - Arizona Microtek, Inc |
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AZP63 데이터시트(HTML) 3 Page - Arizona Microtek, Inc |
3 / 12 page Arizona Microtek, Inc. AZP63 Low Phase Noise Sine Wave CMOS to LVPECL Buffer/Divider www.azmicrotek.com +1-480-962-5881 3 Request a Sample May 2012, Rev 2.1 ENGINEERING NOTES FUNCTIONALITY The AZP63 is one of a family of parts that provide options of fixed ÷1, fixed ÷2 and selectable ÷1, ÷2 modes as well as active high enable or active low enable to oscillator designers. Table 2 details the differences between the parts to assist designers in selecting the optimal part for their design. Table 3 lists the specific AZP63 functional operation. Figure 2 plots the S-parameters of the D input. S-parameter and IBIS model files for the AZP63 are also available for download. Table 2 - AZP51-54 & AZP63 Family Part Number Divide Ratio EN Logic EN pull- up/pull-down Bandwidth AZP51 ÷1 active HIGH Pull-up > 800MHz AZP52 ÷2 active HIGH Pull-up > 800MHz AZP53 Selectable ÷1 or ÷2 selectable selectable > 800MHz AZP54 ÷1 active LOW Pull-down > 800MHz AZP63 Selectable ÷1 or ÷2 selectable selectable ≥ 1GHz Table 3 – AZP63 Functional Operation, ÷1 mode Inputs Outputs Part Number EN_SEL EN D Q Q AZP63 High, NC1 Low, NC1 Low Low High High High Low High X2 Z3 Z3 Low High, NC1 Low Low High High High Low Low X2 Z3 Z3 DIV_SEL Divide Ratio Low, NC1 ÷1 High ÷2 1 Not connected 2 Don't care 3 Tri-State |
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