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AZP63QG 데이터시트(PDF) 7 Page - Arizona Microtek, Inc

부품명 AZP63QG
상세설명  Low Phase Noise Sine Wave/CMOS to LVPECL Buffer/Divider
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제조업체  AZM [Arizona Microtek, Inc]
홈페이지  http://azmicrotek.com
Logo AZM - Arizona Microtek, Inc

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Arizona Microtek, Inc.
AZP63
Low Phase Noise Sine Wave CMOS
to LVPECL Buffer/Divider
www.azmicrotek.com
+1-480-962-5881
7
Request a Sample
May 2012, Rev 2.1
EVALUATION BOARD (EBP53)
Arizona Microtek’s evaluation board EBP53 provides the most convenient way to test and prototype AZP63 series
circuits. Built for the AZP53Q 1.5x1.0 mm package, it is designed to support both dual and single supply operation. Dual
supply operation (VDD=+2.0V, VSS=-1.3V) enables direct coupling to 50Ω time domain test equipment (Figure 7).
VDD (+2.0 V)
Vbp
M1
M2
M3
M4
D
Vbn
M5
21.1mA
21.1mA
16mA
Q
Q
50
50
21.1mA - High
5.1mA - Low
Test
Equipment
Terminations
Output
Stage
VSS (-1.3 V)
Figure 7 - Split Supply LVPECL Output Termination
AC TERMINATION
Clock applications or phase noise/frequency domain testing scenarios typically require AC coupling. Figure 8 below
shows the AC coupling technique. The 200
Ω resistors form the required DC loads, and the 50Ω resistors provide the AC
termination. The parallel combination of the 200
Ω and 50Ω resistors results in a net 40Ω AC load termination. In many
cases this will work well. If necessary, the 50
Ω resistors can be increased to about 56Ω. Alternately, bias tees combined
with current setting resistors will eliminate the lowered AC load impedance. The 50
Ω resistors are typically connected to
ground but can be connected to the bias level needed by the succeeding stage.


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