Arizona Microtek, Inc.

AZT71

Programmable Capacitive Tuning IC

www.azmicrotek.com

+1-480-962-5881

9

Request a Sample

May 2012, Rev 1.2

The EEPROM can be erased by initiating a programming cycle with all DA bits set high, including bit9 and bit10. After

the programming cycle, all the EEPROM bits are set low (logical high) except for the check bit (bit0), which remains

high.

Table 7 – Erase sequence for EEPROM

Step

Action

1

2

Load the programming word bits all high.

3

Set the PV pin to +6V (≥5.6V, ≤6.1V) with the pulse and idle shown in timing diagram (Figure 13)

4

Verify the correct EEPROM contents by reading back the individual bits

t

DA

CLK

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

bit 7

bit 8

bit 9

bit 10

bit0

bit10

loaded last

PV

4µs

min

10ms

min

EEPROM has

been erased

(no capacitors

selected)

≥5.6V,

≤6.1V

Figure 13 – Programming Sequence for erasing the EEPROM

Some existing programming circuits use a current source connected to a 6.5 – 8.0 V supply. That circuit produces an

excessive voltage on the PV pin, which can damage the AZT71. A simple modification eliminates the issue and maintains

full programming compatibility with existing programming methods. A 5.6 V, ½ watt Zener, 1N5232B or equivalent,

placed between the PV pin and ground will limit the voltage while still allowing the programming circuit to generate the

current required for programming fuse link type parts.