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74VHCT02BQ 데이터시트(PDF) 2 Page - NXP Semiconductors |
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74VHCT02BQ 데이터시트(HTML) 2 Page - NXP Semiconductors |
2 / 14 page 74VHC_VHCT02_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 13 August 2009 2 of 14 NXP Semiconductors 74VHC02; 74VHCT02 Quad 2-input NOR gate 4. Functional diagram 5. Pinning information 5.1 Pinning Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate) mna216 1A 1B 1Y 3 2 1 2A 2B 2Y 6 5 4 3A 3B 3Y 9 8 10 4A 4B 4Y 12 11 13 001aah084 2 1 3 5 4 ≥1 6 ≥1 8 10 ≥1 9 11 13 ≥1 12 mna215 A B Y (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 4. Pin configuration SO14 and TSSOP14 Fig 5. Pin configuration DHVQFN14 74VHC02 74VHCT02 1Y VCC 1A 4Y 1B 4B 2Y 4A 2A 3Y 2B 3B GND 3A 001aak052 1 2 3 4 5 6 7 8 10 9 12 11 14 13 001aak053 74VHC02 74VHCT02 Transparent top view 2B 3B 2A 3Y 2Y 4A 1B 4B 1A 4Y 6 9 5 10 4 11 3 12 2 13 terminal 1 index area GND(1) |
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