Data Sheet

AD7609

Rev. A | Page 9 of 36

Parameter

Min

Typ

Max

Unit

Description

Delay from RD falling edge to FRSTDATA low

22

ns

29

ns

20

ns

27

ns

29

ns

Delay from CS rising edge until FRSTDATA three-state enabled

1

2

The delay between the CONVST x signals was measured as the maximum time allowed while ensuring a <40 LSB performance matching between channel sets.

3

A buffer is used on the data output pins for these measurements, which is equivalent to a load of 20 pF on the output pins.

Timing Diagrams

CONVST A/

CONVST B

CONVST A/

CONVST B

BUSY

CS

RESET

Figure 2. CONVST x Timing—Reading After a Conversion

CONVST A/

CONVST B

CONVST A/

CONVST B

BUSY

CS

RESET

Figure 3. CONVST x Timing—Reading During a Conversion

DATA:

DB[15:0]

FRSTDATA

CS

RD

INVALID

V1

[17:2]

V1

[1:0]

V2

[17:2]

V8

[17:2]

V8

[1:0]

V2

[1:0]

Figure 4. Parallel Mode Separate CS and RD Pulses