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AD9257-65EBZ 데이터시트(PDF) 5 Page - Analog Devices

부품명 AD9257-65EBZ
상세설명  Octal, 14-Bit, 40/65 MSPS, Serial LVDS
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제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
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AD9257-65EBZ 데이터시트(HTML) 5 Page - Analog Devices

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Data Sheet
AD9257
Rev. 0 | Page 5 of 40
Parameter1
Temp
AD9257-40
AD9257-65
Unit
Min
Typ
Max
Min
Typ
Max
CROSSTALK
25°C
−100
−98
dB
Crosstalk (Overrange Condition)2
25°C
−92
−94
dB
ANALOG INPUT BANDWIDTH, FULL POWER
25°C
650
650
MHz
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
2 Overrange condition is specified with 3 dB of the full-scale input range.
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.
Table 3.
Parameter1
Temp
Min
Typ
Max
Unit
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
CMOS/LVDS/LVPECL
Differential Input Voltage2
Full
0.2
3.6
V p-p
Input Voltage Range
Full
AGND − 0.2
AVDD + 0.2
V
Input Common-Mode Voltage
Full
0.9
V
Input Resistance (Differential)
25°C
15
Input Capacitance
25°C
4
pF
LOGIC INPUTS (PDWN, SYNC, SCLK)
Logic 1 Voltage
Full
1.2
AVDD + 0.2
V
Logic 0 Voltage
Full
0
0.8
V
Input Resistance
25°C
30
Input Capacitance
25°C
2
pF
LOGIC INPUT (CSB)
Logic 1 Voltage
Full
1.2
AVDD + 0.2
V
Logic 0 Voltage
Full
0
0.8
V
Input Resistance
25°C
26
Input Capacitance
25°C
2
pF
LOGIC INPUT (SDIO)
Logic 1 Voltage
Full
1.2
AVDD + 0.2
V
Logic 0 Voltage
Full
0
0.8
V
Input Resistance
25°C
26
Input Capacitance
25°C
5
pF
LOGIC OUTPUT (SDIO)3
Logic 1 Voltage (IOH = 800 μA)
Full
1.79
V
Logic 0 Voltage (IOL = 50 μA)
Full
0.05
V
DIGITAL OUTPUTS (D± x), ANSI-644
Logic Compliance
LVDS
Differential Output Voltage (VOD)
Full
247
350
454
mV
Output Offset Voltage (VOS)
Full
1.13
1.21
1.38
V
Output Coding (Default)
Twos complement
DIGITAL OUTPUTS (D± x), LOW POWER, REDUCED SIGNAL
OPTION
Logic Compliance
LVDS
Differential Output Voltage (VOD)
Full
150
200
250
mV
Output Offset Voltage (VOS)
Full
1.13
1.21
1.38
V
Output Coding (Default)
Twos complement
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
2 This is specified for LVDS and LVPECL only.
3 This is specified for 13 SDIO/DFS pins sharing the same connection.


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