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ADF4151 데이터시트(PDF) 8 Page - Analog Devices

부품명 ADF4151
상세설명  Fractional-N/Integer-N PLL Synthesizer
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ADF4151
Data Sheet
Rev. B | Page 8 of 28
Pin No.
Mnemonic
Description
22
RSET
Connecting a resistor between this pin and GND sets the charge pump output current. The nominal voltage
bias at the RSET pin is 0.49 V. The relationship between ICP and RSET is
SET
CP
R
I
22.95
=
where:
RSET
= 5.1 kΩ.
ICP = 4.5 mA.
25
LD
Lock Detect Output Pin. This pin outputs a logic high to indicate PLL lock; a logic low output indicates loss of PLL
lock.
26, 27
DGND
Digital Ground. Ground return path for DVDD.
28
DVDD
Digital Power Supply. This pin should be the same voltage as AVDD. Decoupling capacitors to the ground plane
should be placed as close as possible to this pin.
29
REFIN
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resistance
of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.
30
MUXOUT
Multiplexer Output. This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference
frequency to be accessed externally.
31
SDGND
Digital Sigma-Delta (Σ-Δ) Modulator Ground. Ground return path for the Σ-Δ modulator.
32
SDVDD
Power Supply Pin for the Digital Σ-Δ Modulator. Should be the same voltage as AVDDx. Decoupling capacitors
to the ground plane are to be placed as close as possible to this pin.
EP
The exposed pad must be connected to GND.


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