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전자부품 데이터시트 검색엔진 |
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ADP1047DC1-EVALZ 데이터시트(PDF) 31 Page - Analog Devices |
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ADP1047DC1-EVALZ 데이터시트(HTML) 31 Page - Analog Devices |
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31 / 84 page  Data Sheet ADP1047/ADP1048 Rev. 0 | Page 31 of 84 Three load lines address super high line, high line, and low line input voltage conditions. When the rms value of the input voltage is higher than the super high line input (for example, 250 V), the load line is flat, that is, the output voltage remains at VOH, which is independent of the power. To avoid output voltage oscillation when the input voltage is around the super high line level, voltage hysteresis can be programmed using Register 0xFE4D. It is recommended that at least 16 V of hysteresis be programmed. When the rms value of the input voltage is lower than the super high line input but higher than the high line threshold, there is a load line between P1 and P2 in terms of power. The output voltage varies between VOH1 and VOH2 as a linear function of the output power when the output power falls within the range between P1 and P2. The power levels of P1 and P2 are programmable using Register 0xFE44 and Register 0xFE45, respectively. When the power is below P1, the output voltage remains unchanged at VOH1. When the power is higher than P2, the output voltage remains unchanged at VOH2. The bottom load line in Figure 29 applies when the rms value of the input voltage is lower than the low line threshold. The output voltage varies between VOL1 and VOL2 as a linear function of the output power when the output power falls within the range between P1 and P2. When the power is below P1, the output voltage remains unchanged at VOL1. When the power is higher than P2, the output voltage remains unchanged at VOL2. The user can program values for VOH, VOH2, VOH1, VOL2, and VOL1 using Register 0xFE4A, Register 0xFE49, Register 0xFE48, Register 0xFE47, and Register 0xFE46, respectively. SMART SWITCHING FREQUENCY For higher efficiency, the switching frequency of the ADP1047/ ADP1048 can be programmed according to the load power con- dition (see Figure 30). To enable the smart switching frequency feature, set Register 0xFE4F, Bit 3, to 1. POWER fS fSL FULL POWER PTH SWITCHING FREQUENCY Figure 30. Smart Switching Frequency Control The smart switching frequency feature uses two different switching frequencies for heavy load and light load conditions. When the output power is lower than the low power threshold, PTH, the PFC circuit switches at the fSL frequency. When the out- put power is higher than PTH plus power hysteresis, the circuit switches at the normal set frequency, fS. Hysteresis can be programmed in Register 0xFE4E. The user can program the values for fSL and PTH in Register 0xFE1C and Register 0xFE32, respectively. CURRENT LOOP FILTER FOR LIGHT LOAD To achieve low THD under light load conditions, the ADP1047/ ADP1048 offer current loop filter presets for light load opera- tion under both high line input and low line input (see Figure 31). To enable the current loop filter for light load feature, set Register 0xFE4F, Bit 5, to 1. HIGH LINE LIGHT LOAD HIGH LINE LOW LINE LIGHT LOAD LIGHT LOAD INPUT POWER POWER THRESHOLD LOW LINE HIGH/LOW LINE THRESHOLD AC LINE Figure 31. Current Loop Filter at Light Load Condition When the input power drops below the low power threshold, PTH (set in Register 0xFE32), the current loop filter switches to the light load filter after four full line cycles. When the input power goes above PTH plus the programmed hysteresis, the current loop filter switches back to the normal mode filter immediately. This applies to both high line and low line input. PHASE SHEDDING (ADP1048 ONLY) To achieve high efficiency at light load, the ADP1048 can shut down one PWM output under light load conditions. When the input power drops below the low power threshold, PTH (set in Register 0xFE32), one PWM output is disabled. When the input power goes above the low power threshold plus power hysteresis (set in Register 0xFE4E), the PWM resumes operation. To enable phase shedding for the ADP1048, set Register 0xFE4F, Bit 4, to 1. CURRENT LOOP FEEDFORWARD Current loop feedforward is implemented in the ADP1047/ ADP1048 to improve the power factor and reduce THD under light load conditions (see Figure 32). To enable current loop feedforward, set Register 0xFE4F, Bit 6, to 1. + + VAC –VREF + – IL IREF HI (z) DUTY CYCLE Figure 32. Current Loop Feedforward |
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