Edition 1998-07-27

Published by Siemens AG,

Bereich Halbleiter, Marketing-

Kommunikation, Balanstraße 73,

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SLx 24C04

Revision History:

Current Version: 1998-07-27

Previous Version:

06.97

Page

(in previous

Version)

Page

(in current

Version)

Subjects (major changes since last revision)

3

3

Text was changed to “Typical programming time 5 ms for up to

16 bytes”.

4, 5

4, 4

CS0, CS1 and CS2 were replaced by n.c.

5

–

The paragraph “Chip Select (CS0, CS1, CS2)” was removed

completely.

55

WP =

V

11, 12

11, 12

The erase/write cycle is finished latest after 10 8ms.

15

15

Figure 11: second command byte is a CSR and not CSW.

19

19

“Capacitive load …” were added.

20

20

Some timings were changed.

20

20

The line “erase/write cycle” was removed.

20

20

Chapter 7.4 “Erase and Write Characteristics” has been added.