TDA 4916 GG
When the supply to the switch-mode power supply is switched on, the capacitive
displacement current from the gate of the SIPMOS transistor is conducted to the
smoothing capacitor at
S QSIP by the diode connected to VS QSIP. The voltage at
S QSIP may reach about 2.3 V in the process without the SIPMOS transistor being
The diode connected to ground clamps negative voltages at Q SIP to minus 0.7 V.
Capacitive currents which occur with voltage dips at the drain terminal of the SIPMOS
transistor can then flow away unimpeded.
The output is active Low with supply voltages at
S and VS QSIP from about 4 V on. The
function of the diode connected to
S QSIP and the resistor are then taken over by the
The two ground terminals 0V SQIP and 0V GND can lie at different levels. This permits
connections to be made to the SIPMOS transistor in such a way that the drive currents
for the gate do not flow to the source via the current-sensing resistor. The maximum
permissible level differences between 0V GND and 0V SQIP are given under Functional
Range. If greater level differences are anticipated, it is better to join the two terminals.