전자부품 데이터시트 검색엔진 |
|
SL4015BN 데이터시트(PDF) 4 Page - System Logic Semiconductor |
|
SL4015BN 데이터시트(HTML) 4 Page - System Logic Semiconductor |
4 / 5 page SL4015B . System Logic Semiconductor SLS AC ELECTRICAL CHARACTERISTICS(C L=50pF, RL=200k Ω, Input t r=tf=20 ns) VCC Guaranteed Limit Symbol Parameter V ≥-55°C 25 °C ≤125°C Unit tmax Maximum Clock Frequency (Figure 1) 5.0 10 15 3 6 8.5 3 6 8.5 1.5 3 4.25 MHz tPHL, tPLH Maximum Propagation Delay, Clock to Q (Figure 1) 5.0 10 15 320 160 120 320 160 120 640 320 240 ns tPHL Maximum Propagation Delay, Reset to Q (Figure 2) 5.0 10 15 400 200 160 400 200 160 800 400 320 ns tTHL, tTLH Maximum Output Transition Time, Any Output (Figure 1) 5.0 10 15 200 100 80 200 100 80 400 200 160 ns CIN Maximum Input Capacitance - 7.5 pF TIMING REQUIREMENTS(C L=50pF, RL=200 k Ω, Input t r=tf=20 ns) VCC Guaranteed Limit Symbol Parameter V ≥-55°C 25 °C ≤125°C Unit tw Minimum Pulse Width, Clock (Figure 1) 5.0 10 15 180 80 50 180 80 50 360 160 100 ns tw Minimum Pulse Width, Reset (Figure 2) 5.0 10 15 200 80 60 200 80 60 400 160 120 ns tsu Minimum Setup Time, Data to Clock (Figure 3) 5.0 10 15 70 40 30 70 40 30 140 80 60 ns th Minimum Hold Time, Clock to Data (Figure 3) 5.0 10 15 0 0 0 0 0 0 0 0 0 ns tr, tf Maximum Input Rise and Fall Time (Figure 1) 5.0 10 15 15 6 2 15 6 2 30 12 4 µs |
유사한 부품 번호 - SL4015BN |
|
유사한 설명 - SL4015BN |
|
|
링크 URL |
개인정보취급방침 |
ALLDATASHEET.CO.KR |
ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |