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DAC712PK 데이터시트(PDF) 2 Page - Texas Instruments |
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DAC712PK 데이터시트(HTML) 2 Page - Texas Instruments |
2 / 23 page ABSOLUTE MAXIMUM RATINGS (1) A 0 A 1 DAC712 SBAS023A – SEPTEMBER 2000 – REVISED JULY 2009 ................................................................................................................................................. www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION(1) DIFFERENTIAL LINEARITY ERROR MAX LINEARITY ERROR MAX PACKAGE- PACKAGE SPECIFIED PRODUCT AT +25°C AT +25°C LEAD DESIGNATOR TEMPERATURE RANGE DAC712P ±4LSB ±4LSB PDIP-28 NT –40°C to +85°C DAC712U ±4LSB ±4LSB SOIC-28 DW –40°C to +85°C DAC712PB ±2LSB ±2LSB PDIP-28 NT –40°C to +85°C DAC712UB ±2LSB ±2LSB SOIC-28 DW –40°C to +85°C DAC712PK ±2LSB ±2LSB PDIP-28 NT 0°C to +70°C DAC712UK ±2LSB ±2LSB SOIC-28 DW 0°C to +70°C DAC712PL ±2LSB ±1LSB PDIP-28 NT 0°C to +70°C DAC712UL ±2LSB ±1LSB SOIC-28 DW 0°C to +70°C (1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. DAC712 UNIT +VCC to COMMON 0, +17 V –VCC to COMMON 0, –17 V +VCC to –VCC 34 V Digital Inputs to COMMON –1 to +VCC – 0.7 V External Voltage Applied to BPO and Range Resistors ±VCC V VREF OUT Indefinite Short to COMMON VOUT Indefinite Short to COMMON Power Dissipation 750 mW Storage Temperature Range –60 to +150 °C (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. TRUTH TABLE WR CLR DESCRIPTION 0 1 1 → 0 → 1 1 Load Input Latch 1 0 1 → 0 → 1 1 Load D/A Latch 1 1 1 → 0 → 1 1 No Change 0 0 0 1 Latches Transparent X X 1 1 No Change X X X 0 Reset D/A Latch 2 Submit Documentation Feedback Copyright © 2000–2009, Texas Instruments Incorporated Product Folder Link(s): DAC712 |
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