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DAC716U 데이터시트(PDF) 7 Page - Texas Instruments |
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DAC716U 데이터시트(HTML) 7 Page - Texas Instruments |
7 / 16 page 7 ® DAC716 FIGURE 1. DAC716 Block Diagram. FIGURE 2. Equivalent Circuit of Digital Inputs. FIGURE 3. Relationship of Offset and Gain Adjustments. Gain Adjustment Apply the digital input that gives the maximum positive voltage output. Adjust the gain potentiometer or the gain adjust D/A converter for this positive full scale voltage. GAIN AND OFFSET ADJUSTMENTS Figure 3 illustrates the relationship of offset and gain adjust- ments for a unipolar connected D/A converter. Offset should be adjusted first to avoid interaction of adjustments. See Table I for calibration values and codes. These adjustments have a minimum range of ±0.3%. Offset Adjustment Apply the digital input code, 0000, that produces 0V and adjust the offset potentiometer or the offset adjust D/A converter for 0V. Shift Register DAC Latch 14 12 +10V Reference 8 6 7 DCOM +V CC ACOM V REF OUT Gain Adjust 4 SDI 5 SDO 16 2 A 0 3 A 1 1 16 CLK CLR 15 – V CC Offset Adjust 13 NC 11 NC 10 9 V OUT D/A Switches –V CC +2.5V 15k Ω 180 Ω 9.75k Ω 5k Ω R R = 1k Ω: A 0, A1, CLK, CLR, SDI ESD Protection Circuit 6.8V 5pF Digital Input –V CC +V CC 1LSB Range of Offset Adjust Offset Adj. Translates the Line Digital Input FFFF H 8000 H 0000 H Full Scale Range Gain Adjust Rotates the Line Zero Range of Gain Adjust ≈ ±0.3% ≈ ±0.3% + Full Scale |
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