 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
DAC2902 데이터시트(PDF) 5 Page - Texas Instruments |
|
|
||||||||||||||||||||||||||||||
DAC2902 데이터시트(HTML) 5 Page - Texas Instruments |
|
|
5 / 22 page  DAC2902 5 SBAS167C www.ti.com SYMBOL DESCRIPTION MIN TYP MAX UNITS tS Input Setup Time 2 ns tH Input Hold Time 1.5 ns tLPW, tCPW Latch/Clock Pulsewidth 3.5 4 ns tCW Delay Rising CLK Edge to 0 tPW – 2ns Rising WRT Edge tPD Propagation Delay 1 ns tSET Settling Time (0.1%) 30 ns TIMING DIAGRAM t PD t H t LPW t CPW t CW t SET D[11:0] (n) D[11:0] (n + 1) t S I OUT(n) I OUT(n +1) 50% DATA IN WRT1 WRT2 CLK1 CLK2 I OUT1 I OUT2 DIGITAL INPUTS AND TIMING The data input ports of the DAC2902 accept a standard positive coding with data bit D11 being the most significant bit (MSB). The converter outputs support a clock rate of up to 125MSPS. The best performance will typically be achieved with a symmetrical duty cycle for write and clock; however, the duty cycle may vary as long as the timing specifications are met. Also, the setup and hold times may be chosen within their specified limits. All digital inputs of the DAC2902 are CMOS-compatible. The logic thresholds depend on the applied digital supply voltages, such that they are set to approximately half the supply voltage: Vth = +VD/2 (±20% tolerance). The DAC2902 is designed to operate with a digital supply (+VD) of +3.0V to +5.5V. The two converter channels within the DAC2902 consist of two independent, 12-bit, parallel data ports. Each DAC channel is controlled by its own set of write (WRT1, WRT2) and clock (CLK1, CLK2) inputs. Here, the WRT lines control the channel input latches and the CLK lines control the DAC latches. The data is first loaded into the input latch by a rising edge of the WRT line. This data is presented to the DAC latch on the following falling edge of the WRT signal. On the next rising edge of the CLK line, the DAC is updated with the new data and the analog output signal will change accordingly. The double latch architecture of the DAC2902 results in a defined sequence for the WRT and CLK signals, expressed by parameter tCW. A correct timing is observed when the rising edge of CLK occurs at the same time, or before, the rising edge of the WRT signal. This condition can simply be met by connecting the WRT and CLK lines together. Note that all specifications were mea- sured with the WRT and CLK lines connected together. |
유사한 부품 번호 - DAC2902 |
|
유사한 설명 - DAC2902 |
|
|
|
링크 URL |
| 개인정보취급방침 |
| ALLDATASHEET.CO.KR |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
