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54F251A 데이터시트(PDF) 3 Page - Texas Instruments |
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54F251A 데이터시트(HTML) 3 Page - Texas Instruments |
3 / 10 page Unit LoadingFan Out 54F74F Pin Names Description UL Input IIH IIL HIGHLOW Output IOH IOL S0–S2 Select Inputs 1010 20 mA b06 mA OE TRI-STATE Output Enable Input (Active LOW) 1010 20 mA b06 mA I0–I7 Multiplexer Inputs 1010 20 mA b06 mA Z TRI-STATE Multiplexer Output 15040 (333) b 3 mA24 mA (20 mA) Z Complementary TRI-STATE Multiplexer Output 15040 (333) b 3 mA24 mA (20 mA) Functional Description This device is a logical implementation of a single-pole 8- position switch with the switch position controlled by the state of three Select inputs S0 S1 S2 Both assertion and negation outputs are provided The Output Enable input (OE) is active LOW When it is activated the logic function provided at the output is Z e OE (I0S0S1 S2 a I1S0S1S2 a I2S0S1S2 a I3S0S1S2 a I4S0S1S2 a I5S0S1S2 a I6S0S1S2 a I7S0S1S2) When the Output Enable is HIGH both outputs are in the high impedance (High Z) state This feature allows multi- plexer expansion by tying the outputs of up to 128 devices together When the outputs of the TRI-STATE devices are tied together all but one device must be in the high imped- ance state to avoid high currents that would exceed the maximum ratings The Output Enable signals should be de- signed to ensure there is no overlap in the active LOW por- tion of the enable voltages Truth Table Inputs Outputs OE S2 S1 S0 Z Z H XXX Z Z L LLL I0 I0 LL L H I1 I1 L LHL I2 I2 LL H H I3 I3 LH L L I4 I4 L HLH I5 I5 LH H L I6 I6 L HHH I7 I7 H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial Z e High Impedance Logic Diagram TLF9504 – 4 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays 2 |
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