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AM1802 데이터시트(PDF) 5 Page - Texas Instruments |
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AM1802 데이터시트(HTML) 5 Page - Texas Instruments |
5 / 180 page AM1802 www.ti.com SPRS710C – NOVEMBER 2010 – REVISED MARCH 2012 2 Device Overview 2.1 Device Characteristics Table 2-1 provides an overview of the device. The table shows significant features of the device, including the capacity of on-chip RAM, peripherals, and the package type with pin count. Table 2-1. Characteristics of the Device HARDWARE FEATURES AM1802 DDR2, 16-bit bus width, up to 156 MHz DDR2/mDDR Controller Mobile DDR, 16-bit bus width, up to 150 MHz Asynchronous (8/16-bit bus width) RAM, Flash, EMIFA 16-bit SDRAM, NOR, NAND Flash Card Interface MMC and SD cards supported 64 independent channels, 16 QDMA channels, EDMA3 Peripherals 2 channel controllers, 3 transfer controllers 4 64-Bit General Purpose (each configurable as 2 separate Not all peripherals pins Timers 32-bit timers, one configurable as Watch Dog) are available at the same time (for more UART 3 (each with RTS and CTS flow control) detail, see the Device SPI 2 (Each with multiple chip selects) Configurations section). I2C 1 (Master/Slave) Multichannel Audio Serial Port [McASP] 1 (each with transmit/receive, FIFO buffer, 16 serializers) 10/100 Ethernet MAC with Management Data I/O 1 (MII or RMII Interface) USB 2.0 (USB0) High-Speed OTG Controller with on-chip OTG PHY General-Purpose Input/Output Port 9 banks of 16-bit Size (Bytes) 168KB RAM ARM 16KB I-Cache 16KB D-Cache On-Chip Memory Organization 8KB RAM (Vector Table) 64KB ROM ADDITIONAL MEMORY 128KB RAM JTAG BSDL_ID DEVIDR0 Register 0x0B7D_102F CPU Frequency MHz ARM926 300 MHz (1.2V) Core (V) 1.2 V nominal for 300 MHz Voltage I/O (V) 1.8 V or 3.3 V 13 mm x 13 mm, 361-Ball 0.65 mm pitch, PBGA (ZCE) Packages 16 mm x 16 mm, 361-Ball 0.80 mm pitch, PBGA (ZWT) Product Preview (PP), Product Status(1) Advance Information (AI), PD or Production Data (PD) (1) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. 2.2 Device Compatibility The ARM926EJ-S RISC CPU is compatible with other ARM9 CPUs from ARM Holdings plc. 2.3 ARM Subsystem The ARM Subsystem includes the following features: • ARM926EJ-S RISC processor • ARMv5TEJ (32/16-bit) instruction set • Little endian • System Control Co-Processor 15 (CP15) Copyright © 2010–2012, Texas Instruments Incorporated Device Overview 5 Submit Documentation Feedback Product Folder Link(s): AM1802 |
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