CDCLVD2102 datasheet(9/20 Pages) TI1

부품명	CDCLVD2102

상세설명	Dual 1:2 Low Additive Jitter LVDS Buffer

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제조업체	TI1 [Texas Instruments]

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t

PLH3

t

PLH0

t

PHL0

t

PLH1

t

PHL1

t

PHL3

INPx

INNx

OUTP0

OUTN0

OUTP1

OUTN1

OUTP3

OUTN3

t

PLH2

t

PHL2

OUTP2

OUTN2

0V Differential

OUTPx

OUTNx

VOD

Vring

V

OS

GND

CDCLVD2102

www.ti.com

SCAS904A – MAY 2010 – REVISED JUNE 2010

A.

Output skew is calculated as the greater of the following: As the difference between the fastest and the slowest tPLHn

or the difference between the fastest and the slowest tPHLn (n = 0, 1, 2, 3).

B.

Part-to-part skew is calculated as the greater of the following: As the difference between the fastest and the slowest

tPLHn or the difference between the fastest and the slowest tPHLn across multiple devices (n = 0, 1, 2, 3).

C.

Both inputs (IN0 and IN1) are phase aligned.

Figure 9. Output Skew and Part-to-Part Skew

Figure 10. Output Overshoot and Undershoot

Figure 11. Output AC Common Mode

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유사한 부품 번호 - CDCLVD2102

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Texas Instruments	CDCLVD2104	782Kb / 21P	[Old version datasheet] Dual 1:4 Low Additive Jitter LVDS Buffer
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유사한 설명 - CDCLVD2102

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Texas Instruments	CDCLVD2106	919Kb / 22P	[Old version datasheet] Dual 1:6 Low Additive Jitter LVDS Buffer
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CDCLVD2102 데이터시트(PDF) 9 Page - Texas Instruments

CDCLVD2102 데이터시트(HTML) 9 Page - Texas Instruments

유사한 부품 번호 - CDCLVD2102

유사한 설명 - CDCLVD2102

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