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CDCM7005-SP 데이터시트(PDF) 5 Page - Texas Instruments

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부품명 CDCM7005-SP
상세설명  3.3-V HIGH PERFORMANCE RAD-TOLERANT CLASS V, CLOCK SYNCHRONIZER AND JITTER CLEANER
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CDCM7005-SP
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SGLS390E – JULY 2009 – REVISED AUGUST 2012
Table 2. PIN ASSINGMENT (continued)
TERMINAL
I/O
DESCRIPTION
NAME
HFG
Bias voltage output to be used to bias unused complementary input VCXO_IN for single
VBB
18
O
ended signals. The output of VBB is VCC – 1.3 V. The output current is limited to about
1.5 mA.
This output can be programmed (SPI) to provide either the STATUS_REF or
PRI_SEC_CLK information. This pin is set high if one of the STATUS conditions is valid.
STATUS_REF is the default setting.
STATUS_REF or
In case of STATUS_REF, the LVCMOS output provides the Status of the Reference
50
O
PRI_SEC_CLK
Clock. If a reference clock with a frequency above 2 MHz is provided to PRI_REF or
SEC_REF STATUS_REF will be set high.
In case of PRI_SEC_CLK, the LVCMOS output indicates whether the primary clock
[high] or the secondary clock [low] is selected.
This LVCMOS output can be programmed (SPI) to provide either the STATUS_VCXO
information or serve as current path for the charge pump (CP). STATUS_VCXO is the
default setting.
In case of STATUS_VCXO, the LVCMOS output provides the status of the VCXO input
STATUS_VCXO
49
O
(frequencies above 2 MHz are interpreted as valid clock; active high).
or I_REF_CP
In case of I_REF_CP, it provides the current path for the external reference resistor
(12 k
Ω ±1%) to support an accurate charge pump current, optional. Do not use any
capacitor across this resistor to prevent noise coupling via this node. If the internal 12 k
is selected (default setting), this pin can be left open.
LVCMOS output for PLL_LOCK information. This pin is set high if the PLL is in lock (see
feature description). This output can be programmed to be digital lock detect or analog
lock detect (see feature description).
The PLL is locked (set high), if the rising edge either of PRI_REF or SEC_REF clock
and VCXO_IN clock at the phase frequency detector (PFD) are inside the lock detect
window for a predetermined number of successive clock cycles.
PLL_LOCK
52
I/O
The PLL is out-of-lock (set low), if the rising edge of either the PRI_REF or SEC_REF)
clock and VCXO_IN clock at the PFD are outside the lock detect window or if a cycle-
slip occurs.
Both, the lock detect window and the number of successive clock cycles are user
definable (via SPI).
Y0A:Y0B
24, 25,
Y1A:Y1B
29, 30,
The outputs of the CDCM7005 are user definable and can be any combination of up to
Y2A:Y2B
33, 34,
O
five LVPECL outputs or up to 10 LVCMOS outputs. The outputs are selectable via SPI
Y3A:Y3B
37,38,
(Word 1, Bit 2-6). The power-up setting is all outputs are LVPECL.
Y4A:Y4B
42, 43
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
UNIT
VCC, AVCC, VCC_CP
Supply voltage range (2)
–0.5 V to 4.6 V
VI
Input voltage range (3)
–0.5 V to VCC + 0.5 V
VO
Output voltage range (3)
–0.5 V to VCC + 0.5 V
Output current for LVPECL/LVCMOS outputs
IOUT
±50 mA
(0 < VO < VCC)
IIN
Input current (VI < 0, VI > VCC)
±20 mA
Tstg
Storage temperature range
–65°C to 150°C
TJ
Maximum junction temperature
150°C
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2)
All supply voltages have to be supplied at the same time.
(3)
The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
Copyright © 2009–2012, Texas Instruments Incorporated
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