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SN74SSTV32852-EP 데이터시트(PDF) 5 Page - Texas Instruments

부품명 SN74SSTV32852-EP
상세설명  24-BIT TO 48-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS
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TIMING REQUIREMENTS
SWITCHING CHARACTERISTICS
SN74SSTV32852-EP
24-BIT TO 48-BIT REGISTERED BUFFER
WITH SSTL_2 INPUTS AND OUTPUTS
SCES700 – OCTOBER 2007
over operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 2.5 V
±0.2 V
UNIT
MIN
MAX
fclock
Clock frequency
200
MHz
tw
Pulse duration, CLK, CLK high or low
2.5
ns
tact
Differential inputs active time(1)
22
ns
tinact
Differential inputs inactive time(2)
22
ns
Fast slew rate(3)(4)
0.75
tsu
Setup time
Data before CLK
↑, CLK↓
ns
Slow slew rate(5)(4)
0.9
Fast slew rate(3)(4)
0.75
th
Hold time
Data after CLK
↑, CLK↓
ns
Slow slew rate(5)(4)
0.9
(1)
VREF must be held at a valid input level, and data inputs must be held low for a minimum time of tact max, after RESET is taken high.
(2)
VREF, data, and clock inputs must be held at valid voltage levels (not floating) for a minimum time of tinact max, after RESET is taken low.
(3)
Data signal input slew rate
≥1 V/ns
(4)
CLK, CLK input slew rates are
≥1 V/ns.
(5)
Data signal input slew rate
≥0.5 V/ns and <1 V/ns
over operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 2.5 V
FROM
TO
±0.2 V
PARAMETER
UNIT
(INPUT)
(OUTPUT)
MIN
MAX
fmax
200
MHz
tpd
CLK and CLK
Q
1.1
3.1
ns
tPHL
RESET
Q
5
ns
Copyright © 2007, Texas Instruments Incorporated
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