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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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SMJ320LC31KGDM40B 데이터시트(PDF) 9 Page - Texas Instruments |
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SMJ320LC31KGDM40B 데이터시트(HTML) 9 Page - Texas Instruments |
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9 / 54 page  SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006 9 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 functional block diagram 24 Boot Loader Cache (64 × 32) RAM Block 0 (1K × 32) RAM Block 1 (1K × 32) RDY HOLD HOLDA STRB R/ W D31− D0 A23 − A0 RESET IR PC CPU1 REG1 REG2 MUX 40 32 32 32 32 32 32 32 24 24 24 24 BK ARAU0 ARAU1 DISP0, IR0, IR1 Extended- Precision Registers (R7−R0) Auxiliary Registers (AR0 − AR7) Other Registers (12) 40 40 40 40 Multiplier 32-Bit Barrel Shifter ALU DMA Controller Global-Control Register Source-Address Register Destination- Address Register Serial Port 0 Serial-Port-Control Register Receive/Transmit (R / X) Timer Register Data-Transmit Register Data-Receive Register FSX0 DX0 CLKX0 FSR0 DR0 CLKR0 Timer 0 Global-Control Register Timer-Period Register Timer-Counter Register TCLK0 Timer 1 Global-Control Register Timer-Period Register Timer-Counter Register TCLK1 Port Control STRB-Control Register Transfer- Counter Register PDATA Bus PADDR Bus DDATA Bus DADDR1 Bus DADDR2 Bus DMADATA Bus DMAADDR Bus 24 40 32 32 24 24 32 INT(3 − 0) IACK MCBL / MP XF(1,0) VDD(19 − 0) VSS(24 − 0) X1 X2 / CLKIN H1 H3 EMU(3 − 0) 32 24 24 24 24 32 32 32 CPU2 32 32 40 40 Not Recommended for New Designs |
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유사한 설명 - SMJ320LC31KGDM40B |
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