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SN74ACT2440FN 데이터시트(PDF) 8 Page - Texas Instruments

부품명 SN74ACT2440FN
상세설명  NuBusE INTERFACE CONTROLLER
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SN74ACT2440FN 데이터시트(HTML) 8 Page - Texas Instruments

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SN74ACT2440
NuBus
™ INTERFACE CONTROLLER
SCHS010 – D3158, OCTOBER 1988 – REVISED JANUARY 1991
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
8
When MHOLD is tied in common with NREQ and MRDY, only one master cycle is generated. To generate
another cycle, NREQ, MRDY, and MHOLD must be regenerated, which takes additional clock cycles. In the
high-speed mode, the next start cycle is automatically generated. The advantage of this mode is that it produces
faster read/write cycles. The disadvantage is that it shortens the time allowed for the local board to respond to
read data and prepare for the next cycle.
master lock cycles
The ’ACT2440 is designed to support resource locking on the NuBus
™. If the master lock request input (MLREQ)
is taken active (low) when the NuBus
™ request input (NREQ) is sampled, the controller issues an attention lock
cycle after winning arbitration. An attention lock cycle warns all other modules connected to the bus that their
local resources should be locked for the following transactions. The end of the locked sequence is signaled by
an attention null cycle. The timing diagram in Figure 5 illustrates a typical locked sequence.
After the attention lock cycle is issued, normal NuBus
™ master cycles can be performed. If the transfer type must
be changed during a locked sequence, the new transfer code must be latched into the ’ACT2440 by taking
NREQ high for one clock cycle, with MLREQ held low. The MLREQ input remains asserted for the entire lock
tenure. The RQST output remains low for the entire lock cycle. When MLREQ is unasserted, the controller
issues an attention null cycle. If no other masters are arbitrating for the bus, the controller parks on the NuBus
™.
local resource conflict timing
In applications where the local circuitry can be both a master and a slave, conflicts for local resources may
develop. For example, if the local circuitry starts the arbitration process as a master and loses to another master
that in turn accesses the local circuit’s slave resources, then the local circuitry must respond to the NuBus
™ as
a slave and immediately be ready to accomplish a master cycle.
The master ready input (MRDY) provides a throttle mechanism to handle such situations. If this signal is inactive
(high) when the master-state machine wins arbitration, the master-state machine freezes in the current state,
maintaining all arbitration signals until MRDY is asserted low. The timing diagram in Figure 6 shows a situation
where the local board has started arbitration as a master but loses to another master that is attempting to read
or write data from the local resource.
The slave external request status output (SEREQ) signals the local board that another master is accessing the
local board. When the local board is ready to respond, it drives slave grant access (SGNTA) active (low), which
enables data and/or address information to be placed onto the local board. When the local board is ready to
respond, the local acknowledge input (LACK) is driven active (low). This action causes the controller to issue
an acknowledge cycle on the next driving clock edge. For additional details, refer to the section covering typical
slave cycles.
When the local board finally wins the arbitration process, the NuBus
™ master status signal (NMSTR) goes active
(high). The local board responds by taking master ready (MRDY) low, which causes the controller to execute
a normal master read or master write cycle. In applications where the local board is only a master, MRDY can
be tied in common with NREQ for simpler operation.
master timeout cycle
When master ready (MRDY) is used to throttle the controller, a 16-state counter sets a maximum length of time
that the controller will stay in the frozen state after winning arbitration. With NREQ low and MRDY high, this
counter is enabled when the arbitration contest is won. When this timer reaches its maximum count (16), it forces
the controller to issue a NuBus
™ attention null cycle, which in turn signals all other masters on the bus to
re-initiate arbitration. Figure 7 shows the timing diagram for the master timeout cycle.
On rare occasions, the local circuitry may give up on a NuBus
™ request while still in the arbitration process. The
controller detects this situation and issues a NuBus
™ attention null cycle once it has won arbitration.


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