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TMP20AIDRLT 데이터시트(PDF) 10 Page - Texas Instruments |
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TMP20AIDRLT 데이터시트(HTML) 10 Page - Texas Instruments |
10 / 18 page TMP20 SBOS466 – DECEMBER 2009 www.ti.com LAYOUT INFORMATION Figure 15 illustrates a layout of the TMP20 with proper electrical connections and poor thermal The substrate on the TMP20AIDCK package is connections to ground. directly connected via conductive epoxy to the flag which connects pin 2 (GND) on the lead frame. Consequently, pin 2 (GND) is the best lead for a conductive thermal connection to the TMP20 die. In addition, the optimal electrical connection for this pin is ground (GND). Do NOT attempt to connect pin 2 to any electrical potential other than ground. If it is not possible to connect pin 2 to ground, it is also possible to electrically isolate this pin (that is, leave it floating); however, be very cautious in doing this because any noise or electromagnetic interference or radio frequency interference (EMI/RFI) spikes that couple in through this pin can cause erroneous temperature results. Figure 14 shows a proper layout of the TMP20 with correct electrical and thermal connections of pin 2. Figure 15. TMP20 Layout with Proper Electrical and Poor Thermal Connections to Ground Figure 14. TMP20 Layout with Proper Electrical and Thermal Connections for Pin 2 space 10 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TMP20 |
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